A question about formality

[zjwang]

Hi,

I want to use formality to do the hierarchy verification for my design, so i use the write_hirearchical_verification_script command to write out a script, and then i source the scritp. The result told me that there is a block failed and this cause the higher hiearachical block which contains the block all failed.
But when I verify that lower hierarchical block separatly, it is success. Then why the block failed in hierarchical verification?

 

[spauls]

are u using scan stiched netlist or pre scan netlist,

 

[zjwang]

i used scan stiched netlist, and i have set the port test_so don't verify, port test_se to constant 0

 

[masai_mara]

Apart from the DFT insertion you also have to check the interface between blocks and any glue logic between them.

 

[claint]

Yes, DFT or clock tree may change the ports or logic of block.

 

[zjwang]

But the problem is thate when i use the same gate netlist and the rtl netlist of that block and use the same settings to verify them separatly, not in hierarchy, they all passed and reported no failing points.