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Recent content by zhanch

  1. Z

    implementing channel estimation on FPGA

    Hi, guys Who knows how to implement a OFDM channal estimation algorithm, for instance, LS and MMSE, on a FPGA devices. Could you please give me some reference design or academic papers? Cheers,
  2. Z

    Block synthesis in Synopsys DC

    just wonder whether synopsys DC can do block synthesis. For example, there are serveral modules are the same. Can we ask DC just to synthesis one module, and others using the same netlist and sdf. Actually, I know synplify ASIC can do this, not sure whether synopsys can do in the same way...
  3. Z

    Clock Tree Synthesis - CTS

    The tools can automatically do this for you
  4. Z

    synthesis: is my code fully RTL?

    I am afraid you can say in that way. You should check whether the synthesis tools can generate the circuits what you want to design.
  5. Z

    Ideas for final year topic in VLSI and networking area

    Re: need a project title What's the sensor network?
  6. Z

    SoC system level simulation

    Is that the way for industrial project?
  7. Z

    SoC system level simulation

    Hi, guys what's the most popular system level simulation and verification language for the industrial SoC design? SystemC, pure C or system Verilog. Many thanks,
  8. Z

    Looking for Freescale DSP device assembler reference

    Hi, folks Does anyone have the reference of the assembler for freescale's dsp device? Many thanks.
  9. Z

    Active HDL problem: how to display the toolbox ?

    Re: Active HDL problem click the "view" on the top bar
  10. Z

    Linking Matlab files and changing results to linear form

    Re: Need help on Matlab fopen function change the dimension such as A= A' Thanks a lot
  11. Z

    What tool are used for system verilog designing?

    Re: about system verilog modelsim 6.0 or activehdl6.3
  12. Z

    How to implement interpolation using verilog coding

    verilog interpolation You can find lots of paper talking about this on ieeexplore.
  13. Z

    Astro or SOC Encounter?

    I met the CEO of Magma on this year ASPDAC conference. He said the final aim of Magma's CAD tools is cut the ic design flow, from RTL directly to GDSII. But Magma's tools is not mature now.
  14. Z

    suggestion on IC front-end design

    only familiar with EDA tools is not enough. You cannt get any pratical experience from books. Books only can tell you the right direction. Nobody can be an expert when he first come to a field. You must increase ur pratical experience from the industrial projects. anyway, Rome wasn't built in a day
  15. Z

    How to do system design and verfication of video decoding ?

    Re: How to do system design? SystemC is a good choice if u r familiar with C language. Matlab is too high to do system level design. But if u only wanna verify the algorithms, Matlab is easy.
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