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Dear my friends,
I have found a verilog code from this link. But some modules is missing. for example "fp_add". I guess it is a prebuild xilinx ip core. I have two questions.
Am i right?
I cant find the description of this module. Vivado cant specify it. why
Dear my friends,
I have a created a soc project using vivado 2018. I have added an accelerator as an IP to main cpu of soc.
My problem is that when I synthesis the accelerator as a separate project (mode outofcontext) it uses 57000 LUT in synthesis. But when I add it to my design as IP it uses...
I have written a verilog code that fully mapped to a zynq 7z020 fpga. I have only used FPGA side. Is there a estimation of ASIC area of the code for example in 10 NM?
Dear my friends,
I have read the AXI4 standard from xilinx. In this manaul it has menthioned that AXI data bus could be 32, 64 or 128. But actually in the interface only 32bit is supported. I have the Xilinx vivado 2018.2 and use AXI4 as a ip core for ZYNQ (zedboard). Any body can help me to...
Dear
Thank you for your attention.
I know that but i cant download the link!!!!! because the xilinx website said me: " We cannot fulfill your request as your account has failed export compliance verification. "
Do you have the file? Could you please email it to me?
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