ASIC area estimation

[Zerox100]

I have written a verilog code that fully mapped to a zynq 7z020 fpga. I have only used FPGA side. Is there a estimation of ASIC area of the code for example in 10 NM?

 

[ads-ee]

Why would Xilinx provide tools to estimate the ASIC area of a design implemented in their Zynq part?

Xilinx and their investors would rather you keep buying Zynq parts.

If you want to know the ASIC area estimate get a 10nm library and synthesize your Zynq code using that 10nm libraary and use whatever ASIC tools that estimate the size.

 

[dpaul]

It is very difficult to find a 1:1 correspondence. ASICs will report the utilization as the number of gate equivalents and FPGAs will report in terms of LUT*s used (considering other FPGA primitives such as BUF*, MMCM/PLL, DSP-slices, BRAMs, etc are not used).

Some years ago I tried to find an answer and the following thread will be nearest to what you are looking for:

http://forums.xilinx.com/t5/Versal-...gate-equivalent-with-XU-LUTs/m-p/893795#M7385

There are some other threads in the Xilinx forum too related to this subject.

http://forums.xilinx.com/t5/Other-F...-equivalecny-with-ASIC-gate/m-p/855600#M26854

http://forums.xilinx.com/t5/Other-FPGA-Architecture/equivalent-ASIC-gate-count/m-p/945868#M32252

A blog - http://forums.xilinx.com/t5/PLD-Blog-Archived/ASIC-Prototyping-Using-FPGA-Devices/ba-p/132014