Welcome to EDAboard.com

Welcome to our site! EDAboard.com is an international Electronic Discussion Forum focused on EDA software, circuits, schematics, books, theory, papers, asic, pld, 8051, DSP, Network, RF, Analog Design, PCB, Service Manuals... and a whole lot more! To participate you need to register. Registration is free. Click here to register now.

Register Log in

Slicing DSP block in Zynq FPGA. Is it possible

Zerox100

Full Member level 5
Joined
Mar 1, 2003
Messages
317
Helped
21
Reputation
42
Reaction score
10
Trophy points
1,298
Activity points
2,487
Dear my friend,

Today I bring up with new question.

Is it possible to Slice DSP block in Zynq FPGA?

Could anybody answer please

Thx
 

dpaul

Advanced Member level 4
Joined
Jan 16, 2008
Messages
1,356
Helped
289
Reputation
578
Reaction score
283
Trophy points
1,373
Location
Germany
Activity points
10,337

Zerox100

Full Member level 5
Joined
Mar 1, 2003
Messages
317
Helped
21
Reputation
42
Reaction score
10
Trophy points
1,298
Activity points
2,487
I want to use a 18x25 mutiplier as two 8x8 mutiplier;; if it is possible????
 

dpaul

Advanced Member level 4
Joined
Jan 16, 2008
Messages
1,356
Helped
289
Reputation
578
Reaction score
283
Trophy points
1,373
Location
Germany
Activity points
10,337
I don't think it is possible because the operand width is 25x18 in the DSP48E1.
 

TrickyDicky

Advanced Member level 5
Joined
Jun 7, 2010
Messages
6,994
Helped
2,056
Reputation
4,129
Reaction score
2,005
Trophy points
1,393
Activity points
38,366
The Accumulators in the DSP slice can be run in SIMD (single instruction, multiple data) mode, but this prevents the use of the multiplier.
 

Toggle Sidebar

Part and Inventory Search


Welcome to EDABoard.com

Sponsor

Sponsor

Design Fast


×
Top