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Recent content by yans123

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    Maximum voltage on PCI adjacent pins on PCB

    Hello, I would like to plan a test PCB with multiple components that will interface to automatic tester with PCI edge connector. Since I would like to conduct test of up to 300VDC, I want to know what is the maximum voltage allowed between 2 adjacent PCI edge connector on PCB? How is it...
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    BOM/part manager issue with Orcad CIS

    Hello, I attached the pics. 1 of the schematic and the second of the part manager that shows wht happens when I try to access the part on the schematic.
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    BOM/part manager issue with Orcad CIS

    I tried to it but it didn't work. This is very simple PCB, so I see no problem in using occurrences. The only issue is how to "force" the CIS (part manager & BOM) to separate between the occurrences and don't treat the capacitors as multi-part package. Does anyone has an idea?
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    BOM/part manager issue with Orcad CIS

    Hello, I'm trying to convert old PCB to newer version of Orcad. The old PCB was not created with CIS version. The issue I have is reference designators. In the old design, there were blocks of capacitors that were numbered as: A1-1, A1-2.....A1-16 B1-1, B1-2...B2-16 etc.... In the part manager...
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    making parameter dependent on time in Virtuoso

    Hi, I want to make model parameter to be dependent on time, for example resistor resistivity to be function of time. Is there elegant way to do it? Thanks...
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    change model parameter in Cadence Virtuoso

    Thanks for your reply. But I'm doing this for research purpose so I'm using PTM spice file as my model library, and not a complete Virtuoso PDK from a real manufacturer. Is there a way to make parametric analysis on a model parameter? (i.e. to make the sweep on my model parameter). Thanks
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    change model parameter in Cadence Virtuoso

    Hi, I created some ring oscillator structure in cadence virtuoso. I want to test the sensitivity of the frequency to change in the threshold voltage of the transistors. How can I create parametric analysis to show this (i.e. frequency vs. Vth graph) ? Thanks!
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    use Binary adder as subtractor

    OK ... I tried it. when I did the "+1" in Cin it didn't work fine( wrong values) . When i tried it with different adders it worked fine.
  9. Y

    use Binary adder as subtractor

    Hi , I created ppa 8 bit adder (simulation) and now I want to use it as comparator (=~ subtractor). I know that the logic equation for subtractor is: S=A+B'+1. in my adder I have carry in bit. can I use it to be the "+1" , in the subtraction equation? Thanks...
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    Wierd Ring Oscillator problem

    Hi, I created ring oscillator simulation in Cadence Virtuoso . the ring is made of : INVERTER >>INVERTER >>NAND3>>NOR>>INVERTER I pull one of the NOR's gate input to gnd , and 2 of the NAND inputs to vdd so the gates will behave as inverters . I have some very weird problem with my design ...
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    Hierarchy question in cadence virtuoso

    Thanks again for your answers... I use spectre simulation with spice model files from PTM. I didn't find any user guide with explanations on how to that ? What kind of simulation should I do ? Where to put the probes to find out the different leakage currents? some more questions : 8-O I...
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    Hierarchy question in cadence virtuoso

    Thanks , How do I measure the leakage currents ? ( subthreshold , reverse bias pn diddes etc. ) I use the models from PTM . Thanks ...
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    Hierarchy question in cadence virtuoso

    Hi, I created hierarchy in Virtuoso 6.1.x I created the transistors from scratch , I mean my basic cell is just a transistor with pins because I want to simulate my basic transistor with some more adjustments to leakage currents and some reliability issues , and than I built my architecture...
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    simulation error in cadence virtuoso tech file related ( probably)

    Hi , For university project , I used PTM spice model model for 45 nm technology. when I left the width and length of the transistors empty . The results were not good but ths simulation ran fine . after I tried inserting values ( let say L=45n , w=45nm) I got the error : the parameter `xgl`...
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    extracting magic layout to Cadence Virtuoso

    Hi , Is there a way to take layout extraction from magic , and simulate it in Cadence Virtuoso? Thanks ...
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