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Recent content by whitchurch85

  1. W

    Is the term graphic pipeline referring to a harware or software implementation

    I want to know it the term graphics pipeline, is referring to an actual hardware implementation of a pipeline for graphics processing or if it is referring to a sofware methodology.
  2. W

    sorry dont like it

    I just wish there was a seperate section for discussing computer architecture, questions. Apart from that EDA is really very good.
  3. W

    Understanding Open Access and Cadence

    hi guys, I am looking for some good resource, to undersatnd how Cadence , sits on the Open Access Database. Any links or tutorials will be helpful. Thanks
  4. W

    difference between subcircuit and model

    Thanks Keith, So a subcircuit can be made up of lots of .model elements. whereas a .model is the basic fundamental element.
  5. W

    difference between subcircuit and model

    hi, i would like to know what is the difference between a subcitcuit .X and a .Model definition in hspice. thanks
  6. W

    ISA to Microcode to Microarchitecture.

    Guys I want to understand these terminologies correctely. I want to get correction if my understanding of these terms is flawed. ISA = this is the machine language code 0's and 1's generated by a compiler. These opcodes are visible to the programmer of a particular processor. Micro-code = This...
  7. W

    What happens between reset vector ad BIOS

    Thanks Brian for the detailed explanation, helps a lot. Especially about the debug mode
  8. W

    What happens between reset vector ad BIOS

    Thanks, for the info, i would like to get a more detailed book to get into more in this topic. Any chance of knowing where i can get the following books as pdf: Peter Abel IBM PC Assembly Language and programming Rafiq Usman's famous Microprocessor book. I forget the title of this book.
  9. W

    What happens between reset vector ad BIOS

    After i reset/ turn on my computer, CPU executes first instruction from reset vector( eg:- location 0Xffff ) now what happens after this. How does the BIOS take over to perform its POST and pre-boot duties.??? I want to undertand what happens in the gap between the reset vector and the BIOS...
  10. W

    Does the CPU see virtual or physical address, when it works on Data

    Thanks for clarifying the issue. Things are starting to make more sense now.
  11. W

    Does the CPU see virtual or physical address, when it works on Data

    I know we have a page table to convert virtual address to real physical address. Now we have a CPU executing instructctions and reading and writing data into memory. This Data can be in Caches, or in main memory. What address does the CPU see when it writes into Caches or Main memory. Does...
  12. W

    need your valuable suggestion...

    Dont give up, its not a good idea, do that once your OPT is up, besides there migt be some VLSI consulatncy somewhere, if you enjoy the US environ, culture etc, once you go back to India, there is no coming back. If that is not an issue, going to India is not a bad option. But dont sell...
  13. W

    Difference between Verilog and SystemVerilog

    I was going through a SysemVerilog primer, the syntax of both Veriog and SystemVerilog look the same. What is the difference between both?
  14. W

    can SKILL be used in this aspect

    Well it seems that way. I found this script in a tutorial to generate a rectangle Active, using Skilll in virtuosos. I am getting a syntax error though. it did give me the pointer Id for the layout. I am not a computer science guy. but from what i understood it retrieves pointed id for the...
  15. W

    can SKILL be used in this aspect

    Hi, I recently started work on SKILL in cadence. It seems interesting, from what i learnt in the Manual for SKILL everything done on cadence passes via a SKILL Interpreter. I am wondering is it possible to write (SKILL scripts) - (hope the term script is appropriate) to automate a...

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