Difference between Verilog and SystemVerilog

[whitchurch85]

I was going through a SysemVerilog primer, the syntax of both Veriog and SystemVerilog look the same.

What is the difference between both?

 

[koggestone]

https://en.wikipedia.org/wiki/SystemVerilog

 

[k12345k12345]

Syntaxwise SV is backward compatible with verilog. But SV has a lot of new features like classes, interfaces, OOPS concepts, etc.

 

[sudhamahesh70]

There are lot of differences in verilog and SV.

we can say, SV= verilog+ all features required for Verification +assertions.

we have enhanced version of fork-join which is very usefull for parallel processes,
oops, inter-process communications [semaphore and mailboxes] and
also we can define functional coverage which helps in coverage metrics.

Once, if we start SV we can feel the thrill of it.

--Mahesh.

 

[vivek_p]

System Verilog is mainly used for testing and verification. It has constructs similar to Object oriented Programming

Verilog is mainly used for coding designs........................