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Recent content by Wenf.Yeh

  1. W

    Anyone has tutorials for Astro?

    does anyone have some materials on Astro translating Analog Layout to Macro flow?
  2. W

    high "Z" in my netlist simulation?

    Hi all there are several bits of high z in my 25bits of registers, even in case there is a reset signal, but I find them in my netlist. urh.......crazy! someone help me, plz...... Arthur
  3. W

    what is useful skew.how will come useful skew?

    thx,S.Nikhil! I've searching it for a long a time!
  4. W

    Hold time violation in DFT insertion

    Hi guyes I have a design,When I synthesis it without DFT insertion, my design didn't has a hold time violation. But when I synthesis design with the following script,it has worst hold time violation of -30ns in the timing group of sys clock. ### Test Insertion begin ### set...
  5. W

    timin Violations................plz help

    set time violation must be fixed in the pre-layout stage,or u would get a fail design!! slightly hold time violation can be fixed in the post-layout stage. best regards Athur
  6. W

    PrimeTime & Formality

    Hi,Sam What should I do if I want to turn off hold time check in DC? thx! best regards. Arthur
  7. W

    PrimeTime & Formality

    thx Avi, I konw it is not a good idea to editing netlist,but coulde you tell me how can I set variables in DC corresponding to the LEC's problem,or coulde upload some meterials. u know , I'm a freshman in this area. I'm waiting for ur answer to the Qs.1 thx!
  8. W

    PrimeTime & Formality

    Hi guyes, 1. what should I do if I have found sth wrong in my design's hold time using PrimeTime and I want to fix it now(I don't want to fix it in the post-layout progress)? should I dump out some files in the PT, and let DC eat them to resynthesis the design? 2. if I found some thing wrong...
  9. W

    How to insert a driving buffer in a critical path in synthesis?

    synthesis use Encounter,read the UG
  10. W

    Does Positive Slack helps to avoid Setup violations?

    Positive Slack Hi ,mujju433 It's hard to explane pos skew just in words, u can email me,I have a short article about the information u required Best Regards Arthur
  11. W

    Does Positive Slack helps to avoid Setup violations?

    Re: Positive Slack _____________________ _______ ___clk___| |_________________________| ________________________________ __________________________ __data__________________________ X _________________________...
  12. W

    What does LEC stand for?

    LEC? Hi Avimit, I just konw about the traditional ASIC flow, and could you pls email me some materials about the today's ASIC flow ? and in case I get some error in each step,what should I do?
  13. W

    What does LEC stand for?

    lec conformal script Hi Pinkesh, do u mean post-sim can be replaced by LEC ? there is a opinion that SDF back annotated post-sim can be replaced by LEC what do u think about it ? Bset Regards, Arthur
  14. W

    how to write a clock gating code with verilog?

    clock gating code here is a paper hopes help!
  15. W

    What does LEC stand for?

    Hi,guys what is LEC? :cry: what I can do with this "LEC" ?:cry: and how to do ?:cry: Arthur
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