Welcome to EDAboard.com

Welcome to our site! EDAboard.com is an international Electronic Discussion Forum focused on EDA software, circuits, schematics, books, theory, papers, asic, pld, 8051, DSP, Network, RF, Analog Design, PCB, Service Manuals... and a whole lot more! To participate you need to register. Registration is free. Click here to register now.

Register Log in

Hold time violation in DFT insertion

Status
Not open for further replies.

Wenf.Yeh

Junior Member level 3
Joined
Aug 21, 2007
Messages
28
Helped
4
Reputation
8
Reaction score
2
Trophy points
1,283
Activity points
1,475
Hi guyes
I have a design,When I synthesis it without DFT insertion, my design didn't has a hold time violation.
But when I synthesis design with the following script,it has worst hold time violation of -30ns in the timing group of sys clock.

### Test Insertion begin ###

set hdlin_enable_rtldrc_info true
set test_default_scan_style multiplexed_flip_flop
set test_default_period 100
set test_default_delay 0
set test_default_bidir_delay 0
set test_default_strobe 40
create_test_protocol -infer_clock -infer_async

compile -scan
set_scan_configuration -replace false
# Scan Insertion
insert_dft

### Test Insertion end ###

the drc check have been proseeded.

should I fix the hold time violation or just neglect it? or should I do some settings to disable the hold time checking for TE and TI signal?
 

jery_cn

Newbie level 6
Joined
Jul 7, 2007
Messages
11
Helped
1
Reputation
2
Reaction score
0
Trophy points
1,281
Activity points
1,335
DFT Compiler

I think you should set don't douch attribute on TE and TI signals.
thanks.
 

Status
Not open for further replies.
Toggle Sidebar

Part and Inventory Search

Welcome to EDABoard.com

Sponsor

Top