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Recent content by watabe112

  1. W

    verilog code for binary division.....

    can u give me the code....please
  2. W

    verilog code for binary division.....

    can anyone give me the code in verilog on how to divide two binary number.......i need to divide two 24bit binary number......can anyone help me.....
  3. W

    ieee754 subtraction operation.........

    can anyone help me to correct the error.....the output is not right.....here is my code.....
  4. W

    "Reference to vector wire 'out' is not a legal reg or variable lvalue"....

    can anyone help me to correct the error......here's my code... module top( input [31:0]A, input [31:0]in1, input clk, output [31:0]out ); //----------- Begin Cut here for INSTANTIATION Template ---// INST_TAG tambah stage1 ( .a(A), // Bus [31 : 0] .b(in1), // Bus [31 ...
  5. W

    how to code for xilinx ipcoregen...........

    hi.....i want to ask.....if anyone how to solve this.....i'm using xilinx ipcore gen.....addition core......in the core there are 2 input and one output........for example if i have many value as an input......for example i have 5 value.......how i'm going to add it......i'm using...
  6. W

    how to use ip coregen......

    hi...can anyone give me an example on how to write code for xilinx ipcore gen....for example if i want to find mean.....mean=(a+b)/2........so i need add and division module....how i'm going to write the verilog code in order to find the mean....using the 2 core.....
  7. W

    how to use xilinx core generator in verilog code....

    yes....Synchronized the clock.......if i removed that part....what should i write.......can you tell me how to write the stimulus.....and what is stimulus.....i'm quite new....so i don't how to write the stimulus.......can u help me......
  8. W

    how to use xilinx core generator in verilog code....

    one other thing....can you help me...... i want to use the core to find the mean.....where mean=(A+B)/C...........so,my input will be A,B and C....my operation is A+B=result......then result/C (divide by C)..........so i use addition and division coregen......how do i coding it in...
  9. W

    can xilinx ipcore generator be read in VCS compiler........

    i want to know whether can vcs compiler read xilinx ip core gen.....
  10. W

    how to use xilinx core generator in verilog code....

    thanks.....it's work.....one other things....can vcs read this ip gencore.....because i need to do it in dc and icc......
  11. W

    how to use xilinx core generator in verilog code....

    i already try that.....it seems that....the output remain 32bit 0...........the warning still remain the same.....and the output......is still 32bit 0........can u please upload ur folder....so that i can try it......
  12. W

    how to use xilinx core generator in verilog code....

    here is the folder.....
  13. W

    how to use xilinx core generator in verilog code....

    i already try it......it produce an output....but the output is 32bit 0......seems that it don't do the operations......so what should i do.....seems that the input is not attach to the core.......
  14. W

    how to use xilinx core generator in verilog code....

    this is my code....but seems that there is warning....can you help me how to correct it....when i simulate it.....the result won't appear..... module addtop( input [31:0]A, input [31:0]B, input clk, input [5:0]operation_mode, output [31:0]result_mode ); add uut( .a(A)...
  15. W

    how to use xilinx core generator in verilog code....

    can anyone help me.....i'm using ip core generator......floating point addition.....can anyone help me how to use it........because i need to do it in verilog.......i already generate the core.....but i don't know how to use in......i need to add two ieee754 number.....can anyone help me how to...
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