watabe112
Member level 2
hi.....i want to ask.....if anyone how to solve this.....i'm using xilinx ipcore gen.....addition core......in the core there are 2 input and one output........for example if i have many value as an input......for example i have 5 value.......how i'm going to add it......i'm using verilog.....how i'm going to implement it to the addition core that only have 2 input......please anyone help me.....give an example.......