"Reference to vector wire 'out' is not a legal reg or variable lvalue"....

[watabe112]

can anyone help me to correct the error......here's my code...

module top( input [31:0]A,
input [31:0]in1,
input clk,
output [31:0]out

);

//----------- Begin Cut here for INSTANTIATION Template ---// INST_TAG
tambah stage1 (
.a(A), // Bus [31 : 0]
.b(in1), // Bus [31 : 0]
.clk(clk),
.result(out)); // Bus [31 : 0]


// INST_TAG_END ------ End INSTANTIATION Template ---------
assign
A = 32'b00000000000000000000000000000000;

always @(posedge clk)
begin: tambah
end

always @ (posedge clk)
out <= in1 + out;
endmodule

error.......
Reference to vector wire 'out' is not a legal reg or variable lvalue
Illegal left hand side of nonblocking assignment

 

[Alexium]

Re: "Reference to vector wire 'out' is not a legal reg or variable lvalue"....

Try output reg [31:0]out