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how to use xilinx core generator in verilog code....

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watabe112

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can anyone help me.....i'm using ip core generator......floating point addition.....can anyone help me how to use it........because i need to do it in verilog.......i already generate the core.....but i don't know how to use in......i need to add two ieee754 number.....can anyone help me how to code the addition operation using core generator in verilog....please.......
 

blooz

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Once you generate a core add the .xco file to your project ........and look for file with extension .veo it will contain the instantiation template ...just write a top module under which you can instantiate your core all the generated files by coregen will be in the directory ipcore of our project directory

////////////////////////////////////////////////////

The following files were generated for 'floating_point_v5_0' in directory F:\Documents and Settings\fp_alu\ipcore_dir\
floating_point_v5_0.asy: Graphical symbol information file. Used by the ISE tools and some third party tools to create a symbol representing the core.
floating_point_v5_0.gise: ISE Project Navigator support file. This is a generated file and should not be edited directly.
floating_point_v5_0.ngc: Binary Xilinx implementation netlist file containing the information required to implement the module in a Xilinx (R) FPGA.
floating_point_v5_0.sym: Please see the core data sheet.
floating_point_v5_0.v: Verilog wrapper file provided to support functional simulation. This file contains simulation model customization data that is passed to a parameterized simulation model for the core.
floating_point_v5_0.veo: VEO template file containing code that can be used as a model for instantiating a CORE Generator module in a Verilog design.
floating_point_v5_0.vhd: VHDL wrapper file provided to support functional simulation. This file contains simulation model customization data that is passed to a parameterized simulation model for the core.
floating_point_v5_0.vho: VHO template file containing code that can be used as a model for instantiating a CORE Generator module in a VHDL design.
floating_point_v5_0.xco: CORE Generator input file containing the parameters used to regenerate a core.
floating_point_v5_0.xise: ISE Project Navigator support file. This is a generated file and should not be edited directly.
floating_point_v5_0_readme.txt: Text file indicating the files generated and how they are used.
floating_point_v5_0_xmdf.tcl: ISE Project Navigator interface file. ISE uses this file to determine how the files output by CORE Generator for the core can be integrated into your ISE project.
floating_point_v5_0_flist.txt: Text file listing all of the output files produced when a customized core was generated in the CORE Generator.
Please see the Xilinx CORE Generator online help for further details on generated files and how to use them.
//////////////////////////////////////////////////

here is example template

Code:
//----------- Begin Cut here for INSTANTIATION Template ---// INST_TAG
floating_point_v5_0 YourInstanceName (
	.a(a), // Bus [31 : 0] 
	.b(b), // Bus [31 : 0] 
	.operation(operation), // Bus [5 : 0] 
	.clk(clk),
	.result(result)); // Bus [31 : 0] 

// INST_TAG_END ------ End INSTANTIATION Template ---------


then details can be obtained read from the Datasheet . up.jpg
 
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watabe112

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this is my code....but seems that there is warning....can you help me how to correct it....when i simulate it.....the result won't appear.....

module addtop( input [31:0]A,
input [31:0]B,
input clk,
input [5:0]operation_mode,
output [31:0]result_mode
);
add uut(
.a(A), // Bus [31 : 0]
.b(B), // Bus [31 : 0]
.operation(operation_mode), // Bus [5 : 0]
.clk(clk),
.result(result_mode)); // Bus [31 : 0]

endmodule

warning.....
WARNING:Xst:2211 - "ipcore_dir/add.v" line 27: Instantiating black box module <add>.
WARNING:Xst:616 - Invalid property "SYN_BLACK_BOX 1": Did not attach to uut.
WARNING:Xst:616 - Invalid property "SYN_NOPRUNE 1": Did not attach to uut.
 

blooz

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warning produced by XST is not a problem ....they are minor ones ...you can simulate even if these warnings are there ,simulating the generated core should ,One Question , are you using Isim.If you are using Isim most often the problem might be the zoom level in the simulation window ...by default it is order of some .001ns ....just change the zoom level .....to order of 10-20ns .....
 

watabe112

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i already try it......it produce an output....but the output is 32bit 0......seems that it don't do the operations......so what should i do.....seems that the input is not attach to the core.......
 

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blooz

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Ok ,could you please attach the full program directory as zip file so that i can have a closer look at the case .some minor mistake might be there ...
 

watabe112

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here is the folder.....
 

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    blooz

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blooz

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The First error Found is in the top module

Line 42: Module <addtop> does not have a port named <result_mode>.

So the code have to be changed
add uut(
.a(A), // Bus [31 : 0]
.b(B), // Bus [31 : 0]
.operation(operation_mode), // Bus [5 : 0]
.clk(clk),
.result(result)); // Bus [31 : 0]//here you wrote .result_mode(result) just change it to result
..
 

watabe112

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i already try that.....it seems that....the output remain 32bit 0...........the warning still remain the same.....and the output......is still 32bit 0........can u please upload ur folder....so that i can try it......
 

blooz

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I have made a slight change to the testbench also now it works ,output appear something other than zero.
here is the folder it's working.Hope this helps
it's working perfect and you can verify the result with

the help of this site which i found very helpful

h**p://babbage.cs.qc.edu/IEEE-754/32bit.html
 

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watabe112

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thanks.....it's work.....one other things....can vcs read this ip gencore.....because i need to do it in dc and icc......
 

watabe112

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one other thing....can you help me...... i want to use the core to find the mean.....where mean=(A+B)/C...........so,my input will be A,B and C....my operation is A+B=result......then result/C (divide by C)..........so i use addition and division coregen......how do i coding it in verilog.......seems that my code have error....can u check it for me......here is my coding.....

.............................code.............................................

module mean_module(input [31:0]A,
input [31:0]B,
input [31:0]C,
input clk,
output [31:0]result,
output [31:0]mean
);

//INST_TAG
addition uut1 (
.a(A), // Bus [31 : 0]
.b(B), // Bus [31 : 0]
.clk(clk),
.result(result)); // Bus [31 : 0]

division uut2 (
.a(result), // Bus [31 : 0]
.b(C), // Bus [31 : 0]
.clk(clk),
.result(mean)); // Bus [31 : 0]


// INST_TAG_END ------ End INSTANTIATION Template ---------


always @(posedge clk) begin
uut1;
end

always @(posedge clk) begin
uut2;
end
endmodule

.......................................end...................................................

the error

ERROR:HDLCompilers:244 - "mean_module.v" line 47 Name 'uut1' could not be resolved
ERROR:HDLCompilers:244 - "mean_module.v" line 51 Name 'uut2' could not be resolved

...........................................................................
can u check it for me.......
 

mrflibble

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Code:
always @(posedge clk) begin
uut1;
end

always @(posedge clk) begin
uut2;
end


Well, what do you expect that code to do?

Without knowing the rest of your code I'd say remove that bit of code and try again.
 

blooz

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always @(posedge clk) begin
uut1;
end

always @(posedge clk) begin
uut2;
end
endmodule
the section where you have to change the code

it should be removed ... and Just write some stimulus and it should work ...

Do you intend to do some thing Synchronized to clock ?.in later stages .
 

watabe112

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yes....Synchronized the clock.......if i removed that part....what should i write.......can you tell me how to write the stimulus.....and what is stimulus.....i'm quite new....so i don't how to write the stimulus.......can u help me......
 

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use q-notation technique abd do simple addition(eg:gvn a no in decimal value multiply with 32767 and divide it by 3.14666 and convert it into hexadecimal value and add the numbers)thn if u want to get the no mul with 3.1466 and tn div by 32767
 

tanajeek

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i hav also same error after ip core instatniation it gives warning " Instantiating black box module <ip module name>..plz tell me how to tackle this error...i want my code warning free..
 

fpga_freak

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Hello Everyone...!

I am having exact same problem. kindly share the solution please. what changes are to be made to the test bench. Any help will highly appreciated..!

Hoping for an early response. Thanks in advance.




I have made a slight change to the testbench also now it works ,output appear something other than zero.
here is the folder it's working.Hope this helps
it's working perfect and you can verify the result with

the help of this site which i found very helpful

h**p://babbage.cs.qc.edu/IEEE-754/32bit.html
 

mrflibble

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If you have the exact same problem, then you should be able to apply the exact same solution. Problem solved. And for every part where your problem is not exactly the same, I'm afraid you'll have to take some time to explain your exact same problem. If you expect people to be able to help you that is. :) If not, your current description will do.
 

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