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Recent content by vvmalode

  1. V

    Is AMBA AHB bus bandwith 16 times clock frequency??????

    I have read that AMBA AHB bus bandwidth (in bps) is 16 times clock frequency. Is it true? I read this in one of the ppt presentation downloaded from net. I want someone to confirm this. If this is true then if clock frequency is 25MHz then can I assume bus bandwidth to be 400Mbps for my AMBA...
  2. V

    Please explain the concept of BURST TRANSFER IN AMBA AHB

    Hi, I am confused with concept of burst transfer type related to AMBA AHB protocol. (1) If I am using 32 bit data bus then can size of my transfer i.e HSIZE exceed 32 bit? (2)What does 8 beat burst mean and what is maximum transfer size of my data in a burst if my bus width is 32 bit...
  3. V

    Clock frequency, Bus frequency, bus cycle for AMBA AHB protocol?????????

    Hi, (1) How to determine number of bus cycle for read operation/write operation for AMBA AHB protocol. If I say bus cycle required for read /write is 4T states, then is it appropriate to say that for any amount of transfer on the bus the number of T states required is 4? (2) Does clock...
  4. V

    What values should I consider for HCLK and AMBA AHB bus speed?

    Hi, I am implementing arbiter module for AMBA AHB protocol for real time masters in verilog HDL. I want to know what value should I specify for HCLK signal. And what value should I consider for as my bus speed/bus bandwidth/bus rate? At least suggest me the source from where I can get this...
  5. V

    Can I use HSIZE signal from master as an input to arbiter for AMBA AHB?

    Hi, I am implementing arbiter module for AMBA AHB protocol for real time masters in verilog HDL. For that I need to calculate deadline for the real time masters. It will be calculated as: Deadline = Execution time + Arrival time of request + slack(assumed). Hence I need to know the amount of...
  6. V

    How real time masters convey their deadline constraints to arbiter?

    Hi; I am implementing arbiter module for AMBA AHB protocol in verilog HDL. For that I am considering real time masters having constraints in terms of deadline and service cycle. Now I am stuck at a point and want to know how the master convey this constraints to arbiter so that the arbiter...
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