vvmalode
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Hi;
I am implementing arbiter module for AMBA AHB protocol in verilog HDL. For that I am considering real time masters having constraints in terms of deadline and service cycle. Now I am stuck at a point and want to know how the master convey this constraints to arbiter so that the arbiter will do the scheduling and grant the bus to one of the contending master. Does the master send the constraints with the request itself or this constraints are already stored in arbiter?
I am implementing arbiter module for AMBA AHB protocol in verilog HDL. For that I am considering real time masters having constraints in terms of deadline and service cycle. Now I am stuck at a point and want to know how the master convey this constraints to arbiter so that the arbiter will do the scheduling and grant the bus to one of the contending master. Does the master send the constraints with the request itself or this constraints are already stored in arbiter?
