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Hi
I need to design LDO which will work also for retention mode where SPEC for self current is very low.
For regular mode Iself <800u
For low power mode Iself<10u
Somebody have an expirience for such kind of design?
Lets say i can design high power amplifier and switch it for low power mode...
hi
Let's agree that LDO its a circuit with feedback
output LDO cpacitor connected to LDO ouput.
If some circuit has a feedback and goal of the feedback is keep ouput voltage stable and this voltage is changed due to LDO load so feedback will try to return the Vout to nominal Value i.e...
When Vout is going over the desired voltage Vnom the feedback should return this over voltage to Vnom in other word descharge the LDO output capacitor.
In order to discharge capacitor should be the Current to ground but in case Iload=0 how this capacitor going to discharge?
Hi
When LDO Vout go lower LDO current is go higher and Voltage is up but Voutgo up LDO feedback close the pass gate but how this volateg is going to discharge.
there is no discharge current When Iload is very low or = 0 and LDO resitor feedback divider in genral has very low current.
This...
Hi Erikl
First of all thank you for fast response
The example of 50nV/√Hz+50nV/√Hz=100nV/√Hz was only for example for noise buget separation (and of couse you right for unrelated noises)
acuttaly I have noise Spec for each decad and yes PSRR ids different per Frequency.
But from you answer I...
Hi
I have the Noise Spec on LDO output in nV/√Hz
And from this Spec I have to separate to LDO self noise and noise on LDO input with rejection --> PSSR
For Example
10MHz noise =100nV/√Hz
50nV/√Hz--> self noise
50nV/√Hz--> noise from LDO input after PSRR rejection
Now I want to know how to...
Hi
I'm trying to simulate LDO stabilitybut there is som e unclear issue for me
what is LDO load - I mean :
I can put as load ideal current source and sweep on load currrent and check phase margin(PM)
and from other hand I can connect reditor insread the ideal current source and sweep on the...
Sorry for not detiled picture (see new attacment) ,but load of the upper driver chain larger by factor 3 than down chain so there big diffreence between currents.
Pmos gate capcitor is about 200pF
Re: sink source LDO
I need design LDO for 2 inverter chains to chain works between 3.3-1.65 voltage and down chain work 1.65-0V. The LDO should stabiliz 1.65 Voltage .See atached picture
Hi
I’m going to design voltage regulator (LVR) for 2 inverters chains
First chain
VCC=3.3 VSS=1.65
Second
VCC=1.65 VSS=0
I think it should be some kind of push - pull LVR which can supply current and receive current.
Do anybody has experience with this kind of LVR or can refer me to relevant...
I'm LDO designer ,and all stability simulation were with good PM ,but when i add package parasitcal inductance LDO's PM go crasy -LDO not stable at all
Did anybody meet this kind of problem ?
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