LDO dual mode - high power and low power

[vovan76]

Hi
I need to design LDO which will work also for retention mode where SPEC for self current is very low.
For regular mode Iself <800u
For low power mode Iself<10u

Somebody have an expirience for such kind of design?

Lets say i can design high power amplifier and switch it for low power mode - but during the switching LDO output volatge can jump up /fall down and go out from SPEC limits

BTW i have an option to design such LDO with NMOS pathgate (OTA has option for higher VDD )

Thanks

 

[erikl]

Don't you think you can bowl down both modes with Iself<10µ ? An LDO's output power will be determined by the W/L size of the output device; the remainder of the circuit shouldn't change its power (current) consumption distinguishably dependent on power (current) output (provided that it's a full MOS circuit).

Regulation speed just depends on the control amplifier, its feedBack speed, and how fast the amplifier's output current can load the output device's input capacitance. Perhaps a few µA are enough for that?