Continue to Site

Welcome to EDAboard.com

Welcome to our site! EDAboard.com is an international Electronics Discussion Forum focused on EDA software, circuits, schematics, books, theory, papers, asic, pld, 8051, DSP, Network, RF, Analog Design, PCB, Service Manuals... and a whole lot more! To participate you need to register. Registration is free. Click here to register now.

Register Log in

Recent content by vlsichipdesigner

  1. V

    Synchronous Resets in Scan Synthesis

    hi , my 2 cents, The main reason for this the reset synchronziers , clock synchronizers needs to be bypassed during scan-mode, so put a mux , one input of the mux , use reset syn output, other input of the mux(active scanmode select line) , use bypass reset (asynch reset), select line with...
  2. V

    How to get off some cells like "**SEQGEN**" in DC

    Re: How to get off some cells like "**SEQGEN**" in hi, my 2cents, please check whether you had kept set_dont_touch on these registers or designs so that tool could not go ahead in mapping. also, please check your list of set_dont_use cells, some of the cells in the dont use list is what...
  3. V

    [50 pts for real help]Design compiler limits

    hi, my 2cents, DC is a very matured tool, there for decades , seen tons of proven success of plenty of tapeouts to its data points . few technical inputs *Tool can break combinational loops and go ahead, it will saying in the warning that loop is there. *multi mode scenarios can be...
  4. V

    question about determining the system speed

    Re: System Speed hi, my 2cents, What is the longest critical path in your design , means how many stages of logic you have in the path , this you will be knowing in RTL . ck-->Q delay +setup time of the flop + setup margin + logic levels (delays ) < clock period . Give a run based on the...
  5. V

    Scan optimization: is it during scan insertion or ....

    hi, i like the way you think. yes what ever best possible optimization is done at DFT compiler and scan order file is generated. scan order file is given as input to the place and route tool, now based on other physical constraints as you mentioned are taken in to account, and tool does...
  6. V

    Can you tell how the decoupling capacitor works?

    hi, my 2 cents, some detailed diagramatic explanation is available @ https://www.vlsichipdesign.com/index.php/Chip-Design-Articles/decoupling-capacitors.html myprayers, chip design made easy https://www.vlsichipdesign.com
  7. V

    regarding timing convergence

    hi, my 2 cents, what do you mean by timing convergence, is it timing corelation? * how to model wireload models and achieve better correlation and a faster timing convergence after p&r stage. * how to model the onchip variations and what are the various variations to account for and how much...
  8. V

    About Astro: How to insert a power-cut cell?

    hi, i dont know whether this answers your question insertPad "VDD" "m1pad" "vdd1" "PAD" insertPad "GND" "m1pad" "gnd1" "PAD" Using these pad insertion directives, the Synopsys application adds two pads to the design: vdd1 An instance, of the pad cell master m1pad, connected to...
  9. V

    net input transition calcuation

    hi, my 2 cents, i dont know whether i understood the question correctly, just do report_timing -from -to -trans -cap, this will help to know the delay and transition values myprayers, chip design made easy https://www.vlsichipdesign.com
  10. V

    HELP ME FOR verilog code for USB 3.0 AND STATIC TIME ANALYSI

    Re: HELP ME FOR verilog code for USB 3.0 AND STATIC TIME ANA hi, everything you had asked to send to your mail id, what is that you want to do in your project if so, you had asked for tutorial, verilog code and things liket hat. my friend, please search the web, which has tons of information...
  11. V

    methods to eliminate clock skew

    hi, what do you really mean eliminate? in real world clocks will surely have skews, only thing what is there is ways to reduce skew, how to use skew to achieve our results, how to model skews in our flows and win even with that uncertanity in reality, unfortunately we cannot eliminate clock...
  12. V

    Clock_skew - reqiestfor resources

    hi, my 2 cents, This is the command to get the skew of a particular launch flop to a path. report_clock_timing -type skew -from reg1/CP -verbose In order to generalize, get the all_registers, loop it with this command, redirect to a file . this will help . myprayers, chip design made easy...
  13. V

    propagated clocks and shadow latches

    hi, my 2cents, After performing Clock tree synthesis, all the clocks are real clocks, where in the delays in the clock path, to each register will be different, you need to propagate the clock, to know the clock delay, thisi s the need for propagated clocks. shadow registers are used, to...
  14. V

    Isolation cells (hold recent value?)

    hi, my 2 cents, if i understand correctly, these are State retention Cells, which register the previous values, because control registers values are required to be preserved as need basis, to perform analysis and use that data. hope it is useful myprayers, chip design made easy...
  15. V

    power mesh calculation questions ??

    hi , my 2 cents let me help you to understand the equations V=IR R = ρL/A = ρL/w*t, where ρ/t can be treated as Rs => Rs*H/w. whereas A = width*thickness Here you have to assume as Branch current. Iblock*Rs*H/w / (Rs*H/w + Rs*W/w) = Iblock * Rs *H/Rs (H+W) = Iblock *H/H+W where H = height...
See more

Part and Inventory Search

Back
Top