Synchronous Resets in Scan Synthesis

[downloadman]

Hi ,

I have reset synchroniser module in my design.
The asynchronous reset coming from top level is synchronised on different clocks generated internally. From that modules various resets flow to other modules of the design.

I have declared reset signal in the scan command file by the follwing command
set_dft_signal -type Reset -port extRstn.

If I connect the top level asynchronous reset to all the logic, then we are getting full coverage, instead if I connect that synchronous resets, the coverage results are bad. I have the following queries :

(1) whether to keep the clkRst module for the scan synthesis ?
(2) Is it correct to connect Synchronous resets to the modules ,if yes how to declare ?


Thanks in Advance
Downloadman

 

[vlsichipdesigner]

hi ,

my 2 cents,

The main reason for this the reset synchronziers , clock synchronizers needs to be bypassed during scan-mode, so put a mux , one input of the mux , use reset syn output, other input of the mux(active scanmode select line) , use bypass reset (asynch reset), select line with scan-mode, then this issue will be resolved and you can perform scan.

Usually reset-synchronizers/clock-synchronizers wont be in scan-path, if so, lot of care is required, as it should not disturb the other logic to some constant value and screw the whole stuff.

myprayers,
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