question about determining the system speed

[mr_byte31]

System Speed

Hi all
I have a little question about determining the system speed (clock frequency)
Now I have finished my AES system
I wrote all the system in Verilog and then I synthesized it using Synopsys Design Compiler and used TSMC 90nm
now I want to know the max clock frequency that I should use so that the system can run without any violations (setup time, holdup time,..........)

 

[vlsichipdesigner]

Re: System Speed

hi,

my 2cents,

What is the longest critical path in your design , means how many stages of logic you have in the path , this you will be knowing in RTL .

ck-->Q delay +setup time of the flop + setup margin + logic levels (delays ) < clock period .

Give a run based on the estimate of your clock freq .

myprayers,
chip design made easy
https://www.vlsichipdesign.com

 

[mr_byte31]

System Speed

isn't there any thing in the tool that can estimate the clock speed ?

 

[Syswip]

Re: System Speed

Hi mr_byte31,

DC can not estimate any timing without running synthesis. I don't think that DC has built in options to allow to run synthesis until you will have max frequency. You should write DC scripts for it.

Set you clock period (it can be unrealistic for the first time) run synthesis check timing violations. Now you can set realistic clock period.

Bests,
http://syswip.com/

 

[mr_byte31]

System Speed

i think after synthesis it is easy to the tool to calculate the clock frequency
I know it can get the critical path
so why not it can't calculate the clock frequency
I think that precision of mentor can get the max frequency after synthesis

 

[Syswip]

Re: System Speed

Hi mr_byte31,

I don't know about "mentor precision" but in DC you should run compilation several times to estimate max frequency.

You also can set very high frequency and after compilation find the longest timing path for estimating max clock. But it is not recommended. DC doesn't recommend to over constraint the design more then 10%.

In your case (AES core) you can set500 - 550 MHz clock as a starting point.

Bests,
Syswip