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Recent content by vlsi_freak

  1. V

    Stratix5 PLL (Megawizard Query)

    Hi, I had generated Stratix5 PLL (s5_pll) using Megawizard Plugin and the created pll instance is pll_test_0002 with a top level wrapper arouND IT. Generated file is shown below; Code: module pll_test ( input wire refclk, // refclk.clk input wire rst, // reset.reset...
  2. V

    readmemb usage in verilog

    Hi, Please let me know the use of 'readmemb' in verilog. Regards, freak
  3. V

    Verilog delay modelling

    Hi, My verilog code is shown below, module tq ( input a, output reg b); always (*) b = #5 a; endmodule I am unable to make out the waveform, what actually this statement does. Can anyone share your thoughts. Regards, freak
  4. V

    50 Mhz pulse capture in 20 Mhz domain

    Hi FvM, Sorry for the confusion. The requirement is the pulse can be there in every alternate 50 Mhz clock cycle. So in the design, there will be pulse coming from the 50 Mhz domain to the 20 Mhz domain. This pulse stays high for only one 50 Mhz clock and goes low. It can go high again in the...
  5. V

    Help me to code a Bidirectional bus using VHDL or Verilog

    Hi, I am working on an ASIC. Please help me to code a Bidirectional bus using any of VHDL or Verilog. Can anyone share a code for this. Regards, freak
  6. V

    50 Mhz pulse capture in 20 Mhz domain

    FvM, If the pulse gets generated for every 50 Mhz clock, your design fails. Please correct me if i am wrong. Regards, freak ---------- Post added at 10:29 ---------- Previous post was at 10:23 ---------- Hi All, I want to replicate the pulse in the destination 20 Mhz domain. The source...
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    50 Mhz pulse capture in 20 Mhz domain

    Hi, I have a design requirement to capture a pulse signal from a 50 Mhz domain to 20 Mhz. Please let me know, how can i capture these pulse without any pulse is missed. Regards, freak
  8. V

    VHDL Generate loop index

    Hi, I am working on an HDL for an Altera design. I came a situation where i want to increment vhdl generate loop index by 2. An example is show below, LABEL: for i in 1 to CNTR_WIDTH -1 generate REG1(i) <= ORG_REG(i)(1 downto 0); REG1(i+1) <= ORG_REG(i)(3 downto 2); end generate; I...
  9. V

    In DC set_ip_delay or set_op_delay who & how decides val

    Re: In DC set_ip_delay or set_op_delay who & how decides Hi, Input delay depends on the signal coming to your module from external world and similary output delau for output signals. These delay indicates how much percentage of clock is required for external logic so that these signals...
  10. V

    Best book for studying STA by beginner ?

    Best book for STA Hi All, Which is the best book for studying STA in depth, starting from basics. regards, freak
  11. V

    Declaring 2D Port in Verilog

    Hi, Anyone know, how to declare a 2-D port in Verilog. regards, Jaseel
  12. V

    single cycle cdc synchronization

    Can you plz elaborate your q? . Why you are trying to synchronize when it is not a domain crossing ..? regards. freak
  13. V

    is there 8 inputs 1 output circuitry?

    Re: 8 inputs 1 output 8:1 Mux is the answer.
  14. V

    States reduction techniques

    Please refer Digital design by John Wakerly. Its a good book for this topic. Hope it helps. regards, freak
  15. V

    ASP Designware Cells Usage

    Hi, I have many designware components in my library, and in most if the designs i can see sepcific designware components (say mux, gates) are hand instantiated in design. Please let me know, what is the impat, advantages of using a designware component rather coding the same in our design...
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