Help me to code a Bidirectional bus using VHDL or Verilog

[vlsi_freak]

Hi,

I am working on an ASIC.
Please help me to code a Bidirectional bus using any of VHDL or Verilog.
Can anyone share a code for this.

Regards,
freak

 

[std_match]

Re: Bidirectional buffer

It is easy to do in VHDL or verilog, but the ASIC experts say that they don't want this inside an ASIC, only on external pins. Newer FPGA's from Altera and Xilinx can not have bidirectional signals internally, only on external pins.

In VHDL, you use port type "inout" and assign 'Z' when you want to tri-state the drivers, but this might not be true if you design an ASIC. If it is an external pin, the I/O cell probably has a separate "output enable" signal (and separate input and output signals, of course).

Summary:
Don't create bidirectional signals inside the ASIC. Forget how to do bidirectional stuff in VHDL or verilog, and look at the interface of the I/O cells.