# 50 Mhz pulse capture in 20 Mhz domain

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#### vlsi_freak

##### Full Member level 2
Hi,

I have a design requirement to capture a pulse signal from a 50 Mhz domain to 20 Mhz.
Please let me know, how can i capture these pulse without any pulse is missed.

Regards,
freak

#### rca

the first question is, what are the rate/duration of this pulse at 50MHz? Could you elaborate about this pulse waveform?
if your pulse occures each two 50MHz clock cycles (divide by 2 of 50MHz=>25MHz), you could not capture them with the 20MHz.
if you could increased the duration of this pulse (don't impact the design), you could reach a duration require to be detect by a 20MHz clock.
if you could not increased the duration of the pulse, you could used a handshake system between the two clock domains.

#### mikersia

##### Full Member level 2
DLL which will divide clock cycle by whole number intervals (e.g. 1/20MHz:10) can be used to storbe 50MHz pulse. Delay increment can be adjusted to required accuracy.

#### FvM

##### Super Moderator
Staff member
Here's a component that I use for similar purposes. The input pulse ce is assumed to be shorter than a perio of clk.
Code:
library ieee;
use ieee.std_logic_1164.all;

entity ce_sync is
port
(
clk:  in std_logic;
ce:   in std_logic;
ce_s: out std_logic
);
end entity;

architecture rtl of ce_sync is
signal ce_s_int:  std_logic;
signal ce_lat:  std_logic;
begin
process (clk, ce)
begin
IF ce_s_int = '1' THEN
ce_lat <= '0';
ELSIF RISING_EDGE(ce) THEN
ce_lat <= '1';
END IF;
IF RISING_EDGE(CLK) THEN
ce_s_int <= ce_lat;
END IF;
end process;
ce_s <= ce_s_int;
end rtl;
P.S.: To handle possible metastability of ce_s_int, you may want to use a register chain in it's place.

#### vlsi_freak

##### Full Member level 2
FvM,

If the pulse gets generated for every 50 Mhz clock, your design fails.
Please correct me if i am wrong.

Regards,
freak

---------- Post added at 10:29 ---------- Previous post was at 10:23 ----------

Hi All,

I want to replicate the pulse in the destination 20 Mhz domain.
The source pulse is coming from 50 Mhz domain.

The signal is a pulse and it stays for high for only 1 clk cycle (50 Mhz clock)

Regards,
freak

#### FvM

##### Super Moderator
Staff member
If the pulse gets generated for every 50 Mhz clock, your design fails.
Please correct me if i am wrong.
The signal is a pulse and it stays for high for only 1 clk cycle (50 Mhz clock)
Both conditions are mutual exclusive. If the pulse is generated for at least two consecutive or even every 50 MHz cycle, it stays high longer than only 1 clock cycle.

Please reconsider your requirements. You should particularly specify the intended behaviour, if more than one pulses are generated within a 20 MHz clock cycle.

#### vlsi_freak

##### Full Member level 2
Hi FvM,

Sorry for the confusion.
The requirement is the pulse can be there in every alternate 50 Mhz clock cycle.
So in the design, there will be pulse coming from the 50 Mhz domain to the 20 Mhz domain. This pulse stays high for only one 50 Mhz clock and goes low. It can go high again in the third clock cycle.

Can anyone share your thoughts to synchronize this.

Regards,
freak

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