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Recent content by vibhute_r_p

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    Why use PENABLE in APB? Need explanation

    Why use PENABLE in APB? HI, In case of APB 2 spec, there is no ready signal, so in order to do data transfer, master and slave both will use enable signal to know that data transfer is done. However the ready signal is added in APB 3.0 and then ready has to be used along with enable to know...
  2. V

    Challenges in Multi-Core Architecture Verification...?

    In my view multi core architecture is one where the CPU itself has multiple cores (e.g ARM cortex A9 has say 4 cores). The SoC which has multiple CPUs is called as multi processor SoC .
  3. V

    Gate-level Netlist TO RTL Netlist

    rtl and netlist Hi sunil, I agree that we can use DC to do one ASIC netlist to other technology ASIC netlist, But what if i have asic netlist and i want to port that to FPGA.... Such a method is needed for this application. Hi zhide, I had written such perl script as my masters thesis...
  4. V

    Where can I find simulation model of Intel StrataFlash?

    hi, you can use mt28f800b5.v model from free model foundary. I have used this model successfully to test the intel strata flash. Regards, Ramchandra
  5. V

    access to DDR on Spartan 3E Starter Kit

    use the DDR core for www.gaisler.com
  6. V

    Poiwer down in LPC2132 ARM7

    lpc2132 vbat vbat should be sufficient
  7. V

    search for SRAM which can support burst read/write

    search for SRAM See the cellular RAM link below **broken link removed**
  8. V

    designware used in NC-verilog

    Yes..use Gtech models
  9. V

    about SD card clock control

    No ..clock can not be shut down during data transfer. Regards, Ram
  10. V

    Gate-level Netlist TO RTL Netlist

    verilog gate level netlist library IF no tool is giving you the expected result ..you can write simple perl script to do this translation Ram
  11. V

    virtex 2 .... dpRAM with dual writes

    Hi, so far i know from book designs warrirs guide to fpgas, gate cound for latches is less that flip flops. So the fpgas will generally designed with latches with some wrapper to use them as flipflop. will any body come with code where latches are used for dp ram and the wrapper around it...
  12. V

    How to test FPGA VHDL LCD code?

    fpga counter lcd In order to simulate your code for LCD you need to write LCD behavioural model and then test it.
  13. V

    NC Launch and Xilinx ISE

    I am thinking that the if you are using cadence tools in unix and you xilinx libs are in windows C:. How the cadence will be able to see this. I suggest copy these folders in unix and give that path in cds.lib
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    What is the main use of PERL in VLSI?

    why do you prefer perl in vlsi Hi, here is a elaborated answer - 1. In schools and colleages, the vlsi tools used will be generally GUI based. You do design, compile, simulation etc with the help og GUI. 2. In practical, guys in companies prefer to use command line intarface of the vlsi...
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    virtex 2 .... dpRAM with dual writes

    There are several model codes avaliable in xst user manul of xilinx. For dual port ram with two read + write ports there is a code. If you use that with ise , i am sure it will give you dual port ram. How ever same codee i tried with synplify pro. It is giving error "No such flipflop exists". In...
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