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Hi ccw27,
thanks.
i was reading the grey and meyer's book. I remember the difference between voc and vcm have to be small, otherwise the control device will be out of sat region?
common mode dc analysis
Hi all,
I am trying to do dc analysis of open loop OTA. at the beginning I was doing dc differential sweep to make sure all the device working in saturation region, after I has been told to use CMFB to set up the operation point, I am kind of confused: how to...
dc analysis of OTA
Hi all,
I am trying to do dc analysis of open loop OTA. at the beginning I was doing dc differential sweep to make sure all the device working in saturation region, after I has been told to use CMFB to set up the operation point, I am kind of confused: how to...
Re: opamp problems again
I was just thinking I was the only encounter such problems. just want to know how do you guys solve the problems like this. one more thing is like when I was transfer my desgin based on pspise(level 1), m5 m7 and m3(m4), m6 keep the ratio, either m7 or m6 will be out...
attached is the opamp, I was having some problems( short channel)
1. the textbook and most people are talking about the ratio of M5 M7 and M3(M4) and M6. I was using bsim3 level 1 model without any problems, but transfer to cadence tools, with more sophiscated model, the ratio has to be...
I was doing parameter analysis, setting the width of driver nmos of second stage as the parameter, doing dc sweep in cadence, there is really no much margin for the size. I mean sometimes, the size has to be exact to make sure the device in sat region. that's why I was worrying that it might...
thanks for your response. you are right. I just mean the input nmos size range(in saturation region) is very small, it is very possible in linear region considering 10%-30% deviation.
thanks again.
I was trying design a two stage ota, the second stage was using a input common source nmos and a pmos current source load. Once I fixed the size fo the pmos. the input device Nmos is very sensive to the size, I mean a little bit deviation of size will drive the nmos to linear region?--which I...
hspice pd
thanks chunlee, you mean it is normal to get the warning like this? i was trying to extract a hspice netlist from cadence tool, it did have ps pd value. Compare the capacitance, there are some differences. I just thought the hspice should generate some pd value, which should depend...
warning: pd = 0 is less than w.
it is said that hspice will calculate the junction capcitance automatically with w, L only. for the warning, seems it won't calculate the Cj correctly assuming Pd=0?
or my hspice is outdated?
thanks
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