vhdl00
Junior Member level 2

I was trying design a two stage ota, the second stage was using a input common source nmos and a pmos current source load. Once I fixed the size fo the pmos. the input device Nmos is very sensive to the size, I mean a little bit deviation of size will drive the nmos to linear region?--which I don't think a robust design.
any suggestions?
any suggestions?