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Recent content by Vaibhav Sundriyal

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    Effect of Drain-source voltage on NMOS operation

    I have been trying to understand the NMOS operation through various online tutorials but I am getting stuck in understanding the effect of increasing drain voltage on the flow of current and the channel length. I did understand that at similar drain and source potential current does not flow and...
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    System verilog on Quartus synthesis issue

    module blockingbad(input logic clk,a,b,c,output logic y); logic x; always_ff @(posedge clk) begin y=x|c; x=a&b; end endmodule For the above Sysverilog snippet, the quartus 13.1 synthesizes a netlist shown above. But when I interchange...
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    System Verilog Modelsim issue

    `timescale 1ns/1ps module example(input logic a,b,c,output logic y); logic ab,bb,cb,n1,n2,n3; assign #1{ab,bb,cb}=~{a,b,c}; assign #2 n1=ab&bb&cb; assign #2 n2=a&bb&cb; assign #2 n3=a&bb&c; assign #4 y=n1|n2|n3; endmodule The above code snippet assumes that inverters have delay of 1 ns, AND...
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    nMOS passing 1's poorly

    Thanks much for your reply. Doesn't drain=0 means that drain is connected to GND? Am I correct in assuming that by passing 0 or 1 means applying input 0 or 1 at the gate terminal? Thanks
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    nMOS passing 1's poorly

    Hi, I came across the statement in a digital design book that "nMOS transistors pass 0's well but pass 1's poorly" and "pMOS pass 1's well but 0's poorly". What exactly do these statements mean and why is it so? Also, what is the reason that AND and OR gate can't be simply formed but they have...
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