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System Verilog Modelsim issue

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Vaibhav Sundriyal

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`timescale 1ns/1ps

Code Verilog - [expand]
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module example(input logic a,b,c,output logic y);
 
logic ab,bb,cb,n1,n2,n3;
assign #1{ab,bb,cb}=~{a,b,c};
assign #2 n1=ab&bb&cb;
assign #2 n2=a&bb&cb;
assign #2 n3=a&bb&c;
assign #4 y=n1|n2|n3;
endmodule



The above code snippet assumes that inverters have delay of 1 ns, AND gates have delay of 2 ns and
OR GATEs delay of 4 ns. When I simulate this code in modelsim, it shows delay of 1 ns for ab,bb, and cb but delay of
4 ns for n1,n2 and n3
? Why is it so? Shouldn't the delay be 2 ns.

Thanks
 
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