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System verilog on Quartus synthesis issue

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Vaibhav Sundriyal

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Code:
 module blockingbad(input logic clk,a,b,c,output logic y);
        logic x;
        
        always_ff @(posedge clk) begin
        y=x|c;
        x=a&b;
        end
        endmodule


1.jpg

For the above Sysverilog snippet, the quartus 13.1 synthesizes a netlist shown above.

But when I interchange the ordering of calculation of y and x, I get a synthesized netlist shown below.


2.jpg


Why exactly am I getting a different netlist? I know it has got to do with the blocking assignment "=" but I can't understand the change in number of flip flops. Can anybody explain it to me.

Thanks
 

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