Newbie level 4
module blockingbad(input logic clk,a,b,c,output logic y); logic x; always_ff @(posedge clk) begin y=x|c; x=a&b; end endmodule
For the above Sysverilog snippet, the quartus 13.1 synthesizes a netlist shown above.
But when I interchange the ordering of calculation of y and x, I get a synthesized netlist shown below.
Why exactly am I getting a different netlist? I know it has got to do with the blocking assignment "=" but I can't understand the change in number of flip flops. Can anybody explain it to me.