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Re: how to genetate timing and synthesis models of hard macr
Thank you ! IF I also want to generate synthesis models of a hard macro so that I can Integrate it into the top RTL module and sysnthesis the whole system, can you tell me how to do that, I mean, in what EDA tools? Thanks again!
I am reading a book about soc. And I dont know how to genetate timing and synthesis models ( of hard IP core) for synthesis when you want to produce a hard macro. Perhaps it is generated by an EDA tool or other method? Can tell me something about it? thanks a lot!
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