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Recent content by thiagu_comp

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    How to fix problem in my Verilog code

    There can not be an always statement within another always statement. In your code, there is an if stmt inside always and then again another always within that if stmt. Completely wrong way to code. Also make sure whether you want to use that procedural assign stmt inside first always.
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    ASM2BIN error in system verilog simulation

    I am compiling a system verilog code with Active-HDL tool. I get an error which says "Error: ASM2BIN_1297". It does not give any more information. The code looks ok to me. Can someone explain what kind of error is this?
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    Efficient simulation method for video processing FPGA?

    Thanks for the replies. To simulate only significant places and to jump ahead is being evaluated already. But it seems to be a difficult approach. A prototype is already available. We had already got to see the video on the screen. But we can not validate all parts of the code. So we want to use...
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    Efficient simulation method for video processing FPGA?

    I am trying to simulate a video processing FPGA. It processes HD resolution videos (1920x1080). Its very hard to simulate by providing this video input, as it takes about 4 days to send one frame of data (i.e., (1920+100)x(1080+45)=2272500pixels, 30bits each). Due to this limitation, its hardly...
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    ASIC emulation technique - explenation requaierd

    Hi, Can someone explain ASIC emulation in detail? I know that it is quick method to validate the ASIC design before fab. It involves porting of original design to hardware and driving the stimulus. This increases the speed of verification compared to simulation. How is it different from...
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    Scenario - Short on FPGA pins

    Hi, This is a question from electrical behavior point of view. What will happen when 2 output pins of the FPGA gets short and driving complementory logic? Lets consider that the 2 pins are LVCMOS. One driving Logic high and the other logic low. Is it like a power-gnd short, as there are no...
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    digital or analog ??? for beginner

    You can try icarus verilog or verilator. h**p://www.icarus.com/eda/verilog h**p://www.veripool.org/wiki/verilator
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    digital or analog ??? for beginner

    I don't understand what you mean by analog embedded system. Also, "better" is a very subjective word. It varies depending on the measuring unit. If you would like to have challenge in what you work on, then analog is good compared to digital. In terms of the industry, analog is a small sector...
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    VHDL concatenation and integer-to-single-bit Question

    vhdl concatenation 1) Concatenation can be done as below example: ******************************************** ****signal test:std_logic_vector(7 downto 0);**** ****signal test1 : std_logic_vector (3 downto 0);**** ****test1 <= b"1010";**** ****test <= (7 downto 4=> '0') & test1;****...
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    Selecting different include files in verilog

    include verilog 1 --> There is no need to refer to which include file has the specific task. If the file containing the task in included before calling the task, that is enough. 2 --> It depends on what is written inside the file which is included. Syntactically, it is not wrong.
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    how to make code not readable ?

    modelsim ngc When you simulate, are these libraries properly referenced. There are switches like "-lib". Refer vsim command reference in modelsim.
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    PAR successfull, simulation fails

    This is possible. For example, if there is reset recovery / removal issue, this cant be found unless the specific timing for the signal is captured in the timing constraint. There is a possibility that your reset in testbench, violates this timings and a warning is generated. Can you please...
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    Post map simulation in Xilinx ISE 10.1

    xilinxise 10.1 there is a switch in command vsim. I think -sdfwarn. In GUI also, in start simulation window, you can find check boxes which will be something like "diasable sdf errors to warnings" and like.
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    output signal as input (feedback) in verilog

    Re: feedback input Connect output to feedback input with a buffer to avoid timing issues.
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    Post map simulation in Xilinx ISE 10.1

    xilinx ise mapper -k Hi, check if sdf warnings and errors are not disabled in the simulation. if they are disabled, you will not see any errors.
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