VHDL concatenation and integer-to-single-bit Question

[dohzer]

vhdl concatenate std_logic_vector

I've got two (probably simple) VHDL questions.

Firstly, I've got a std_logic_vector signal I want to concatenate with a certain number of zeros to pad it out.

	constant SMALL_WIDTH : integer := 4;
	constant LARGE_WIDTH : integer := 8;

	...

	signal small_signal : std_logic_vector(SMALL_WIDTH-1 downto 0);
	signal large_signal : std_logic_vector(LARGE_WIDTH-1 downto 0);

	...

	large_signal <= ???

What would I put where the ??? is to take "small_signal" padded with zeros in the upper four bits and assign it to "large_signal"?
I could write...

	large_signal <= "0000" & small_signal;

... but if I change the width of each signal, I'd have to change the number of zeros accordingly.
I'm assuming the solution I'm after would involve some sort of "(LARGE_WIDTH downto LARGE_WIDTH)" statement, combined with "others => '0'", but I really don't know the syntax to use.


My second question is to do with converting an integer to a single bit.
Is there a simple way to use a single bit from an integer type variable's binary representation and assign it to a signal?

	signal sig1,sig2,sig3,sig4 : std_logic;

	...

	for count in 0 to 16 loop
		sig1 <= <bit_0_of_count>;
		sig2 <= <bit_1_of_count>;
		sig3 <= <bit_2_of_count>;
		sig4 <= <bit_3_of_count>;

	...

	end loop;

Is there a single line assignment I can use to assign the bits of "count" to their respective signals, or do I need to use another temporary vector to convert count to std_logic and then split the bits out from that?


PS. Sorry if this is the wrong forum... I noticed it is for "device specific VHDL/Verilog/SystemC questions" but wasn't sure where non-specific HDL questions should go.

 

[thiagu_comp]

vhdl concatenation

1) Concatenation can be done as below example:
********************************************
****signal test:std_logic_vector(7 downto 0);****
****signal test1 : std_logic_vector (3 downto 0);****
****test1 <= b"1010";****
****test <= (7 downto 4=> '0') & test1;****
********************************************
2) I am not sure if this can be done in a single line. VHDL is a structured language. These kind of type casting are not automatic.

 

[dohzer]

counting bits in vhdl

Thanks for the reply thiagu_comp. Exactly what I was after with the concatenation question.