Scenario - Short on FPGA pins

[thiagu_comp]

Hi,
This is a question from electrical behavior point of view. What will happen when 2 output pins of the FPGA gets short and driving complementory logic? Lets consider that the 2 pins are LVCMOS. One driving Logic high and the other logic low. Is it like a power-gnd short, as there are no loads except the pass transistors of the CMOS in the path? Are there protection circuits available in the FPGA (Xilinx)? I see that there are some ESD diodes in the IOB architecture of Xilinx Spartan3E. Will this be of any help during this condition?

 

[farhada]

Hi,
My personal experience is that most of the output drivers of the FPGA are pretty rigid and tolerate to be shorted as long as they are in the same standard, but if you have different standards for the pins, it may damage the output driver of the one driving it high if the current exceeds the maximum rating of the pin.

Cheers,
/Farhad