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Dear all,
I am working on an analog IC design project using TSMC 130nm technology. I have all the schematic, layout, simulation models but missing LVS, DRC rules for layout verification (assuraDRC.rul, extract.rul, compare.rul). Does anyone have these files? Can you please share with me if...
@KD_353: Can you please clarify little bit more. I installed Cdesigner 09 2011 - SP2. I am using Fedora 16 64 bit. And I am having the same problem as you had
Hi all,
I used Cadence Chip Assembly router to do auto routing, when the process is done, it created all the connections, but also generated some unknown rectangles, some are in via 10 layer(????), some in unknown layers.
My question is what are they? I saw them before but didnt notice much...
I used Tetramax to generate test patterns for a full adder design. After finish, I showed the first pattern, and receive the following figure. I really dont understand how to read it. I thought a pattern contains a set of inputs. But here I see 3 bits for one input ????.
What do they mean here?
Hi all,
I am using TetraMAX to generate test patterns for a full adder code. The problem is at the stage "Write Patterns", Synopsys no longer let us the patterns in Verilog or VHDL, you will receive the error "write_patterns -format verilog_single_file is obsolete; command ignored". I can only...
From Library Manager. Select Edit -Library Path (or maybe File - Library Path, i am not sure about this). You will see Library Path window, then add the path of your library there
@digi The purpose of this simulation is to determine the size of PMOS so the on-resistance of PMOS and NMOS are the same when transistors on.
With the Vin I swept it from 0-1V; Vdc = 1V as well. So if the simulation can run, I would see something similar to this picture(Vdd here is 5V)...
Hi all,
I am doing a parametric analysis on an inverter by using Spectre. The PDK used is GPDK045 from Cadence.
The circuit and setting are shown in tha t.
My question is beside W(The Width of PMOS), what are other 3 variables(fw, P, iP) come from? What are they? When I point at them and...
Hi all,
I am using ASITIC to design an inductor. I used sweep command to find inductors satisfy given parameters. The command ran fine, but when I checked the output file, its empty :-(.
Does anyone have experience in this situation. Can you give me some helps
Thanks
The attached pic is the...
Hi all. I am having a similar question. I have two sine sources(1V-30Mhz and 1V-32Mhz). I wanna use an analog multiplexer to select between these two. The MUX i am using is based on this pdf www.fairchildsemi.com/ms/MS/MS-555.pdf.
However the output signal showed a big distortion. My question...
Hi Milad-D.
What do u mean by DC simulation, How can I do that? Can you explain more about that. Do I have to connect the transistor with something or just transistor itself?
Hi all,
I am working on a RF project. I am using Cadence Virtuoso 6.1. I need to know the threshold voltage(Vth) and gain parameter(K' = u. Cox) from a transistor model in a library of a PDK. For examle I am using GPDK045, I want to know Vth and K' of cell NMOS1v. How could I do that? I need...
Hi vfone. So in the circuit above, the oscillator is running in saturation region, isnt it? I read in some IEEE papers, they said its very hard to calculate amplitude for Vout. I am really confused now.
I tried with Idc=10ma, W/L = 2285, the Vout = 4.8x2(p-p) ( I think the oscillator in...
Tks vfone, and fvM. I did change the idc to 10mA, and the voltage increased. But why do we have this chane? Can you explain little bit more for me please?
And if i want to get exactly 1V(p-p), wat should I change, are there any equations to calculate this
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