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@ThisIsNotSam
please do the later part of synthesis using Design Compiler or RTL compiler (without any library support) and paste the result here. I don't have access to these tools any more.
If i am wrong, i would humbly accept it :)
@ThisIsNotSam
Please provide a proof of your claim. I hope you understand that we are talking about ASIC synthesis and not FPGA synthesis as we are in ASIC forum.
I am looking into the following code on github. I know verilog and this code is in VHDL. So please help me make sense of it.
https://github.com/Architech-Silica/Designing-a-Custom-AXI-Master-using-BFMs/blob/master/HDL_sources/Synthesis_Sources/AXI_master_transaction.vhd
I have a few questions...
@ThisIsNotSam
Synthesis will not infer an adder if synthesis tool is not aware of any library that has adders. In the absence of an adder library, Synthesis will just create gate netlist ( consisting of AND, OR, XOR gates etc) that will achieve the functionality of an adder
I am trying to learn VHDL and struggling with some of its basics. The question is as follows:
Process statement is described to contain code that runs sequentially (one line after the other). I want to ask why can't one run concurrent code in a process statement (means all lines execute in...
you have to use +access+rwc on the command line and dump using VCD or .shm format.
If you want to just get the hierarchy, i would recommend you look at
https://www.veripool.org/wiki/verilog-perl
On this page, look at Verilog::Netlist. It would be very useful if you look at its documentation...
No you don't have to do it. You should just define period. To begin with, don't use set input and set output delay. They can cause unnecessary confusion and debugging.
Later on, you can use these.
Hi friends,
I want to know how can i find out worst case timing of a sub-module of a Verilog design using Synopsys design compiler.
Please let me know if you have any questions.
Dude you are complicating the design by adding constraints like set_load etc. On first run do without these.
- - - Updated - - -
Here is what you need
module adder_reg
(
input A,B,Cin,clk,rst,
output Cout,
output reg Sum_reg
);
wire Sum;
always @(posedge clk or posedge rst)
begin...
I have not seen adders described like this before.
Why don't you do register the inputs A and B
always @(posedge clk)
begin
A_reg <= A;
B_reg <= B;
end
then do addition as combinational logic
assign {cout,sum} = A_reg + B_reg + cin;
then register the sum output
always @(posedge clk)...
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