Welcome to EDAboard.com

Welcome to our site! EDAboard.com is an international Electronics Discussion Forum focused on EDA software, circuits, schematics, books, theory, papers, asic, pld, 8051, DSP, Network, RF, Analog Design, PCB, Service Manuals... and a whole lot more! To participate you need to register. Registration is free. Click here to register now.

AXI4 master bus functional model implementation

Status
Not open for further replies.

tariq786

Advanced Member level 2
Joined
Feb 24, 2004
Messages
562
Helped
67
Reputation
134
Reaction score
52
Trophy points
1,308
Location
USA
Activity points
3,043
I am looking into the following code on github. I know verilog and this code is in VHDL. So please help me make sense of it.


https://github.com/Architech-Silica.../Synthesis_Sources/AXI_master_transaction.vhd

I have a few questions from the above code

  • Can you help me trace the code or what would an equivalent verilog code look like? What is connected to what?
  • Can you help me make a block diagram of the code?
  • what is the use of FIFO? I mean to connect AXI master to AXI slave, can't one connect the appropriate signals directly as shown in the picture? What purpose does FIFO serve? What happens if it is removed?
 

Attachments

  • axi_master_slave_block.jpg
    axi_master_slave_block.jpg
    38.4 KB · Views: 17
Last edited:

dpaul

Advanced Member level 5
Joined
Jan 16, 2008
Messages
1,548
Helped
308
Reputation
616
Reaction score
309
Trophy points
1,373
Location
Germany
Activity points
11,494
I didn't look into all the details, but this is what I have to say...

1> Can you help me trace the code or what would an equivalent verilog code look like? What is connected to what?
Ans: It is a fairly large amount of code and costs time. Unless you are willing to pay, I doubt anyone here will be willing to do it for free.

2> Can you help me make a block diagram of the code?
Ans: I see it is well documented - https://github.com/Architech-Silica...master/designing_a_custom_axi_master_rev1.pdf
You can easily study the VHDL entity blocks and make a connection block diagram yourself.

3> what is the use of FIFO? I mean to connect AXI master to AXI slave, can't one connect the appropriate signals directly as shown in the picture? What purpose does FIFO serve? What happens if it is removed?
Ans: Generally if master and and slave are working with the same clk then the need for buffering (using FIFOs) does not arise. But there might be other reasons (as I didn't look deeply into the code).

Note that they are using a BFM to which the AXI Master is connected. This is different from a 'real' slave connected to the AXI Master.

- - - Updated - - -

If you are just learning how AXI master and slaves work, then I would recommend this:
https://github.com/ShepardSiegel/hotline/tree/master/doc/axi_examples
 
Status
Not open for further replies.

Similar threads

Part and Inventory Search

Welcome to EDABoard.com

Sponsor

Top