what type of adder is used to implement 4bit A+B during synthesis?

[kaushikrvs]

can we select an adder we want to use in particular or should we design it?

 

[ThisIsNotSam]

synthesis will infer an adder for you if you say nothing. if you want absolute control over it, you better use a designware/chipware library

 

[tariq786]

@ThisIsNotSam

Synthesis will not infer an adder if synthesis tool is not aware of any library that has adders. In the absence of an adder library, Synthesis will just create gate netlist ( consisting of AND, OR, XOR gates etc) that will achieve the functionality of an adder

 

[ThisIsNotSam]

@ThisIsNotSam

Synthesis will not infer an adder if synthesis tool is not aware of any library that has adders. In the absence of an adder library, Synthesis will just create gate netlist ( consisting of AND, OR, XOR gates etc) that will achieve the functionality of an adder

Synthesis will infer an adder whenever it sees a '+' sign in your code, and implementation varies for sure.
Either way, OP is asking about adder architecture, not the components that can be used to make an adder.

 

[tariq786]

@ThisIsNotSam

Please provide a proof of your claim. I hope you understand that we are talking about ASIC synthesis and not FPGA synthesis as we are in ASIC forum.

 

[ThisIsNotSam]

@ThisIsNotSam

Please provide a proof of your claim. I hope you understand that we are talking about ASIC synthesis and not FPGA synthesis as we are in ASIC forum.

You have got to be kidding me.

module proof(a,b,c)
input a;
input b;
output reg c;

always @(*) begin
c = a + b;
end

endmodule

use this in genus/rtl compiler/dc. turn all the debug messages on, highest level. you can literally see the tool saying ADDER INFERRED in the log. implementation varies, as explained.

 

[tariq786]

@ThisIsNotSam

please do the later part of synthesis using Design Compiler or RTL compiler (without any library support) and paste the result here. I don't have access to these tools any more.

If i am wrong, i would humbly accept it

 

[kumar_eee]

exciting war here!!!... waiting for the final conclusion.