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Recent content by take_care00

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    Modelsim gives an unexpected simulating result,why?

    Hi skykanny, echo47 code is works fine. Synchronous logic is supposed to be cleared/preset before its state is allowed to change. BTW, this is the same problem with you second code.Think about this: "what is data_out state at time zero"? You are assuming data_out is initialized to zero so...
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    Is this a bug of ModelSim or a bug of my design

    Hi presto, Your solution is correct but your interpretation is not. Because of the sys_clk <= wb_clk_i; assignement the VHDL standard requires that sys_clk change be scheduled to 1 delta cycle after a change in wb_clk_i signal. So, Modelsim is following the correct behavior. Remember that in...
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    Writing testbench in verilog or e language?

    Hi wilfwolf, The answer dependes on how much money you can spend and how big is your design. If you are verifying a multi-million gates ASIC the best choices today are E or Vera (In 2 years from now it will probably be SystemVerilog). But from your e-mail it seems to me you are doing block...
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    gather information of code coverage tools

    I don't have experience with modelsim code coverage but synopsys code coverage tool is not very good. It is ok if you are doing small blocks but for large projects surecov from Verisity is much much better. Take care.
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    Looking for documents about cordic transformer

    Re: Cordic transformer look at xilinx website. Specially look at the cordic spec in the core generator manual. The spec has a good reference on how cordic works and what the xilinx cordic IP core can do. Also look at www.opencores.org. Lots of good reference and synthesizable cordic IP cores...
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    IBM O18 CMOS decoupling capacitor

    pcdcap Hi uncle_urfi, Do you have any paper about fractal capacitance that you could forward to me? Regarding the upper limit in decoupling capacitance are ratio, IBM doesn sign off the project if you violate their rule. Take care.
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    decoupling mos capacitor

    Hi all, poly-poly capacitance is mainly used in analog design to compensate multiple stage amplifiers for example. Take care.
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    Alert:Design reuse is good to employer but evil to employee

    Re: Alert:Design reuse is good to employer but evil to emplo Hi gam, True. But unfortunately I don't see any way back. If you know a way out of this mess, please share it. :-)) Take care.
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    Opinions on using Cadence Ultrasim for simulation

    Re: C@dence Ultr@sim Hi Vitamin-C, Yes. They are pretty much the same "class" of simulator. These new family of simulators are generally called fast Spice simulators because they are much faster than the second generation Spice-like tools such as HSPICE and SPECTRE. Besides, they can also...
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    how many guys use magma to do layour design

    Tanner tools are cheap and quite ok but I think Cadence IC (with Mentor Calibre for LPE) is my golden environment. Just recently some people in my company started using Magma. They seem pretty happy with the results. Take care.
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    What are the best LPE tools ?

    Re: The best LPE tools ? Do someone has experience with calibre and Assura 3.1? Which one is more accurate? and which one is the fastest? Take care.
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    Opinions on using Cadence Ultrasim for simulation

    Re: C@dence Ultr@sim I wonder if someone has more information about the others competitors of HSIM such as Synopsys/nanosim, Cadence/ultrasim and Evercad/ADiT. As far as I know, Nassda is the only vendor that shows lots of data on their website (**broken link removed** and **broken link...
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    Comparision Spectre HSpice HSim

    Hi, Did anyone compared/used the latest HSIM version which is called by NASSDA as HSIM Plus? According to Nassda the upgrade is provided free of charge for customers with maintenance agreement. The benchmark published in their website (**broken link removed**) is very impressive. Did someone...

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