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x-hdl crashes...
Have anyone tried the tool named vhdl2verilog from Alternative System Concepts Inc, is that possible to convert testbenches written in VHDL to verilog?
glitch free clock switch
use glitch-free clock selector.
The idea is to switch the clock when the orginally selected clock line are at logic 0, wait for 2 clock cycle or so, then ramp up to the newly selected clock.
report_area unit
from DC report_area result, how to convert that unit to gates?
e.g,
Combinational area: 2503906.000000
Noncombinational area: 16571702.000000
I know nothing about how a bus transaction is handled.
I wish to learn it from scatch, for example, what means master, what means slave, etc.
Could anyone share some ideas what and where I can start with?
What book I should read to understand it if I have no previous experience?
Re: how to detect a pulse from a fast clock domain to a slow
Of course the two clocks are asynchronous and it is a single bit signal that does not need a FIFO to handoff.
I know how to use a 2 DFF edge detector to detect pulse from a slow clock domain to a fast one. Can anyone tell me another version of the edge detector that can do the fast-to-slow?
I thought I would stretch the pulse for 5-10 cycles if the clock frequecy between the two are 5-10 times...
FYI, Dont forget what the engineering and engineer are all about.
Few IC designer engineers are working 100% for fun and loved to work overtime.
IMHO, most of them are doing this as a way to make a living and earn big bucks.
On the forum, it seems tons of people are eagle to search for and learn...
For this, you guys will see your fate as an ASIC design/verification Engineer, i.e., You will die sooner or later within 5-10 years! The jobs are moving to India, China, ..., better be prepared for another big career transition at your 40s unless you dont care leaving North America...
Our company has purchased some EDA tools which were not being used for now. I was wondering if we can rent the software to some other companies that is in need of this?
Anyone know the legal procedures to do this?
Do we have to let the original EDA tool vendor know about this?
Is there a...
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