X-hdl crashes when translating the risc5x core from opencore

[davorin]

x-hdl crashes...

Trying to translate the risc5x core from opencores when browsing the source directory x-hdl-3.2.40 just crashes...

Also trying to convert file by file it mostly results in:

"syntax error in line xxx
attribute <--
returned token is 265"

the line leading to this error:

attribute RLOC of u_lut : label is "R" & integer'image(loc(i)) & "C0.S1";


Is this x-hdl tool any serious tool or just sort of simple vhdl2verilog translator?

 

[Santa]

Re: x-hdl crashes...

At 5K$ , at least its price is serious. :wink:

I used it to make some Verilog to VHDL conversions and it worked
albeit it needed quite a lot of hand crafting to correct the readability
of the code. The worst was the fact that the comments were put at
senseless places in the translated code.

The version I tested was 3.2.28 probably. It is about
one year old now. I did not work with 3.2.40.

 

[eltonjohn]

Re: x-hdl crashes...

Hi
x-hdl is SERIOUS ,.is THE BEST thing out THERE .. but if what you want to translate, is poorly written or at least WIRD ..strange things may happen ..
I noticed that to many files included is a POTENTIAL problem .
But over all is THE BEST thing .. I have use it ..and it really produces from
a synthesizable core another synthesizable core ..There is some times a need to tune the INPUT CODE becasue it may LOOP !. at least with the version i'using .. But once again IS THE BEST !

 

[ydao]

x-hdl crashes...

I've faced such problems but when I try another version of x-hdl, I get a proper result.

 

[the_penetrator]

Re: x-hdl crashes...

x-hdl is serious indeed...

however i had the smae problem when converting some ASIC lib from Verilog to VHDL...

this was due to the large file size. So i got a script from the web to split the Verilog files into 1 module per file and everything got from there alright

the_penetrator©

 

[angjohn]

x-hdl crashes...

can anyone tell me what are the thing needed to be watch out of after convert vhdl into verilog ( what i mean is modification needed) !! i need to know it because i know vhdl only and now i am learning verilog only so can anyone help me out with this , please !!!!

 

[eltonjohn]

Re: x-hdl crashes...

x-hdl is a program that translates fairly well synthesizable code to synthesizable code .. So in your case being a starter probably will find problems migrating Testbenches . So stay away from that!

 

[angjohn]

x-hdl crashes...

can anyone tell me how to translate vhdl design (that were consists of many different modules to form the design) using X-HDL into verilog because i cannot compile the translated verilog source code. please can anyone help me out ????
10q in advance!!!

 

[sweesw]

x-hdl crashes...

Have anyone tried the tool named vhdl2verilog from Alternative System Concepts Inc, is that possible to convert testbenches written in VHDL to verilog?

 

[angjohn]

x-hdl crashes...

below is the problem that i experienced during translating vhdl code into verilog, can anyone tell me what it mean by Can't find translated component ! please !!!

// <<X-HDL>> Can't find translated component 'Comparator'. Module name may not match
Comparator U_Comparator (OutR0, OutCMP);
// <<X-HDL>> Can't find translated component 'RAM'. Module name may not match
RAM U_RAM (RBUS, INMAR, CLK, Z[9], MBUS);