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about TSI(Time slot interchanger) design?

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zcg

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Where can I get some hardware design guide ? Can any kind people do me a favor? I am really a new man in TSI field.
 

is that for SONET/SDH applications?
 

nobody answer me? I just want to know how to design input/output buffer. As you known,each channel can be set on different data rate( 2.048Mb/s,4.096Mb/s.....) and the rate of input channel may be not macth with that tranmit channel. So there will be many individual fifos for data store. It will occupy much hardware resource(i.e 32 input channels, 32 output channels).

Is there a economic arithmetic ?

Thanks a lot!!!
 

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