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I am going to build a new Linux box for EDA simulation recently.
I plan to use intel i3/i5 4-core CPU to install RHEL 4.0, but i am worrying that whether I will encounter compatible problems or difficult-to-solve HW driver issue or not?
Can anyone who had the...
Compared to convential PAD structure, the ESD ckt is put under PAD. So the dimension of I/O pad is reduced. (because in the conventional PAD structure, the ESD ckt can't be put under PAD, so need more area for ESD ckt)
transmission gates-asic
Sometimes we use the same size of PMOS and NMOS for easy layout. Besides, the junction capacitance is another consideration,too.
The most easy way is to use advanced process. Because core voltage can be reduced, and power is propotional to V square.
Besides, in most SoC design the embedded SRAM is almost the power-hunger monster. The advanced process is more flavor due to its area and power in terms of embedded SRAM,too.
Dear My friend,
I don't think that you can find the part with 8-channel 10-bit 80MSPS ADC. If possible, you should use 8pcs ADC to fulfill your requirement.
May you kindly let us know what kind of application you plan to build ??
Thanks,
Besides the etching process effect, some optical effect during fabrication has more impact, specially for deep sub-micron technology. More uniform metal density helps the lithography.
Design compiler can translate your gate-level logic design into real cell-based design with cells from library. These cells are composed with real transistor-level circuit with specific sizes and connection.
I/O Design
The main focus on general-purpose of I/O design is reliability. Like ESD and Latch-up. The circuit design and layout concepts are almost around these 2 topics. Unfortunately, the reliability issues can't be simulated by Spice. Although the design and layout guidelines are provided by...
Usually the I/O PAD provided by foundary is too big.
Some company will design their own I/O PAD for area consideration.
There are many books and IEEE papers talking about this topic. You may find them via google.
The whole chip ESD design/consideration is more than just I/O PAD itself. Most...
Usually software reset can't really reset the whole HW FSM which is responsible for the software execution.
But HW reset can reset the whole HW FSM (including SW FSM if any).
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