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Recent content by sumit_techkgp

  1. S

    AC Simulation for SC Circuits in spice

    hspice ac simulation Hello All, We use pac to analyze the ac response of switch cap circuits in spectre. Is there any way to analyze ac-response of switch caps in spice ? Best Regards, Sumit
  2. S

    The question about DC synthesis!

    Hi chenzhao.ee, The problem is not with the tool, it is with your dc script!. U have declared reset signal at the top level and that did not continue because some combinational logic in its path. Declare top level reset as set_false_path -from. This will solve ur problem as per tool is...
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    Verilog doubts about sensitivity list code

    Verilog doubts Hi Vikas, there will be an or gate on the next two sensitive list member. This should not pose any DFT issue as the reset signal entering the flop will be muxed, so i dont see any such issue. But one thing i want to pint out, U should not write that. Any bug or issue is difficult...
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    need help on some DFT problem

    What is the tool u are using? Well u can can define scan chain order. That is possible with every tool
  5. S

    Write Matlab code for FIR

    matlab fir coding Get the coefficients.....and then write a difference equation to use it
  6. S

    Why first order modulator limited to 1-bit quantizer?

    U have a DAC. One bit DAC is a simple switch. More than one bit involves nonlinerity. Thats the reason. One bit circuit has lesser nonlinearity.
  7. S

    Designing DC energy meter using 89C51 micro

    DC energy meter sample input current and voltage and convert synchronously into digital. multiply them and then make a low pass filtering on them to get the dc power(the cut-off of this filter should be your harmonics frequency u want to measure), then convert this number into BOT. Thingsa are...
  8. S

    How to minimize glitch in Verilog RTL coding ?

    minimize glitch well try to write a verilog code where delay balancing is possible during synthesis, and balance the delay during synthesis
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    query in gated clocks

    Hey, this is another suggestion, from ur DC save a svf script and later read it using formality. These changes will be accepted by formality
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    Cadence Skill function for changing the layer properties

    Cadence Skill Ask Cadence, they made lot of changes in SKILL recently.
  11. S

    Using insert_pads command in DC

    insert_pads in DC Modify your RTL and insert pads there and link the library. That is more better and effective way as u dont wanna optimize it, rather for constraining and analyzing the design
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    Design Mismatch after synthesis

    Hi, This is a common behavior. The RTL simulation is a 0-delay simulation, whereas netlist simulation is a delayed simulation. So when delay comes into picture these kind of probs are observed. To avoid them u need to ensure that these probs dosent arises by design, i.e. in RTL. Modify your...
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    Why first order modulator limited to 1-bit quantizer?

    You can use a multibit quantizer. Where are u using, it depends on that!. What is the application ?
  14. S

    who can tell me "$sign" system task ?

    Wanna add something, these two tasks are synthesizable and very handy to use especially when u design DSP
  15. S

    fixing frequency in post synthesis simulation

    There is no way u can improve. Please check whether the constraints are applied properly or not. Still if u get such problems, I think u need to pipeline the datapath. Also check wheter the ports are registered or not, this is very important as u are trying to synthesize in a little higher speed!
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