query in gated clocks

[vsrpkumar]

Is gated clocks verified by DC formailty.I am using gated clock with AND gate and enable signal synchronised in the negative edge of the clock.How to verify in DC formality.Thanking you
Kumar

 

[fpga_asic_designer]

clock gating logic is always a good way to save power.
in formality setup, set verification_clock_gate_hold_mode any

hope it helps

Is gated clocks verified by DC formailty.I am using gated clock with AND gate and enable signal synchronised in the negative edge of the clock.How to verify in DC formality.Thanking you
Kumar

 

[sumit_techkgp]

Hey, this is another suggestion, from ur DC save a svf script and later read it using formality. These changes will be accepted by formality