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Re: nmos grounding
Not all the source of NMOS should be connected to ground. If you place a psub contact next to a NMOS cell, the LVS tool will recognize it as a NMOS device. The "incomplete net" error maybe for you don't connect all the contacts together
Ok, if we have to get an intuitive understanding about the result:Rout = gm*rds*R
we can do it like this:
the output resistance of current sink without degeneration Rs or Re is rds, with the current variation of ΔI, the Vgs remain unchanged but the output voltage will rise ΔI*rds.
the case with...
I'm confused whether MOM cap is fabricated in one metal layer with the interdigitation style or two metal layer with the interdigitation style?
I can't understand with timof's "via connection".
Thank you for your attention
I think two inverters can obtain the transformation。if the power supply voltage is 1.8.In the first stage,a diode-connected PMOS could be cascaded between the PMOS and the power supply to gurantee the cut-off of PMOS when the input signal is 1V.then the second inverter is the general one with...
Re: gain of this amp
I think the gain is 1，because U1 amplify the difference of the outputs of the full-differential pairs，the stage combined by J2 and J3 has the same gain with the stage combined by J1 and J4，let's denotes the gain as -A1，the gain of u1 was expressed as -A2 which can be...
Re: Plotting Vth against L
hello，I do the simulation as you given, but I can't understand the last line
"have a line such as 'save * sigtype=all' an include file", Can you explain how to set in spectre?
Thank you very much!
I supposed that the curve is absolutely normal for the standard model. The effect of channel length modulation and Vth which will decrese with Vds will make Ids increase with the Vds, while the effect of hot carrier will degenerate the Ids. As a result, the two powers will fight for the major...
Re: bandgap reference
you'd better check the dc point of the apamp making sure the correct function of locking the input voltage the same.
according to the curves, the temperature at Tc=0 changed because of the current flowing through the transistors. This is just my guess.
Would you like to...
can you tell me how you can get the symbol of the extracted inverter_lay?Don't you check your layout with Calibre or other tools？
then,I view your question as the netlist errors.Would you like to attach the netlist extracted from the layout?
We can disscuss the questions concerning analog IC...
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