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Recent content by siboy

  1. S

    Clock driver/buffer question

    I have a chip with 1Vpp 50MHz sine-wave-clock output, but my another chip need a 3.3Vpp square-ware input. How can I easily realize this transition on the PCB? Or are there any clock drive/buffer chips for advice？Please tell me the chip's type or send me the datasheet if there are any suitable...
  2. S

    Help! Frequency jump when PLL open loop

    Thank you ! Hi! FvM! Open loop modulation is often used in FSK/GFSK modulation(such as bluetooth). When the signal is modulating the PLL is in open state. Hi! AdvaRes! I had tried using small current. It didn't have any help!
  3. S

    Help! Frequency jump when PLL open loop

    500khz n- frequency pll Both of you are right. 1. with time the capacitance of the filter will see their voltage decreasing because of the leakage. The leakage satified my spec. It only decrease less than 100KHz in 50ms. 2. Each system with negative feedback (even a simple opamp) will loose its...
  4. S

    Help! Frequency jump when PLL open loop

    frequency jump I want to use my PLL to do open loop modulation. When I break the loop(CP's output), the PLL's freqency jump up about 500KHz. My VCO's KV is 100MHz/V, so I guess the Loop Filter's voltage changeing about 5mV. So what's reason? Are there any good papers about it? Thanks!
  5. S

    How to measure PLL's lock time?

    how to measure pll Thank you! I means can I use spectrum analyzer to measure this? And how to do it ? Is it accurate? The minmum sweep time of my spectrum analyzer is 50ms.
  6. S

    How to measure PLL's lock time?

    pll lock time The chip is a tranceiver, the pll's loop filter ans VCO is in the chip. I can only measure the PA's transmiting spectrum, or I can measure the receiver's leaking spectrum. So how can I measure the PLL's lock time ? (The simulated lock time is about 90us) Thanks!
  7. S

    Question about CML divider

    current mode logic divider My divider is a normal CMOS cml divider formed by two cml latch. The tail current is a normal CMOS transistor. I used 2 CML buffer as the load. I used another CML buffer to drive the divider. VDD is 1.8V, and the input of the CML divider is about 400mVpp. The divider...
  8. S

    Question about CML divider

    cml cmos divider Thank you! The output voltage swing is 400mVpp. The divider doesn't work @ss, its output swing is only several mVpp. So how can I make it work @ ss?
  9. S

    Question about loop filter in PLL

    Thank you! Why a charge pump can't drive a resistor dircetly? The loop filter without the buffer is a 3rd order loop filter usuallly used in PLL.
  10. S

    Question about CML divider

    cml divider I made a CML divider. It can easily work up to 4GHz @tt. But when I change the section to ss, it doesn't work anymore. Even I reduce the input freq to 2GHz/1GHz/500MHz or increase the current, it doesn't divide. I guess the problem maybe oscillation startup, so I increas the...
  11. S

    Question about loop filter in PLL

    The loop filter adds a unit gain buffer after the 2nd cap. What's the effect of the unit gain buffer?
  12. S

    input sensitivity simulation

    Increase/Decrease the input frequency till the divider can't work correctly. Then you get the high/low boundary. Right?
  13. S

    Question about CML divider

    I made a CML divider. It can easily work up to 4GHz @tt. But when I change the section to ss, it doesn't work anymore. Even I reduce the input freq to 2GHz/1GHz/500MHz or increase the current, it doesn't divide. I guess the problem maybe oscillation startup, so I increas the simulation time and...
  14. S

    Help about crystal's start time!

    So you means: no matter the external reset is long enough, you do add the delay to the reset time. Right? Generally how many clk's cycles do you add? Thank you very much!
  15. S

    Help about crystal's start time!

    Thanks! FvM! My opinion is similar with you. I've already designed a POR circuit which produce a reset pulse(Reset_POR) about 50us. And I will use a counter to count the clk_osc's posedge and produce another reset pulse(Reset_OSC). Then do 'OR' operation to the two signals to get my finite...
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