Help about crystal's start time!

[siboy]

Generly, how long for a 10MHz crystal oscillator to oscillate?
And how about a 40MHz?
Is it accurate for using spectre to simulate? Because I use a initial current(about 500nA) for the inductor (in crystal), acturally the osc may start by its noise current, I don't knnow wether the simulation's start can be trusted.

 

[ricklin]

Usually several hundreds microns to several mili-seconds. The simulation can not conclude all real conditions, xtals may have same RLC equivelants but different mechanic characteristics .

 

[siboy]

Thanks!
Usually growing with the crystal frequency, the start time decrease, right? Is it realistic to ocillate within 50us? I want to decide reset time for digital circuit. After the reset time, the osc need to output rectangle wave to be the digital circuit's clock. So I don't know if I can trust the spectre's simulation result.

 

[ricklin]

usually 50us is not so reliable. The start up time may varies very much with power up scheme, xtal mechanics or so. I'm not familiar with digital integration, why not just use some synchrous reset when you do care the startup time.

 

[leehying]

50us is not reliable!!

I think you should change your design to someone that the start up time is not cared.

 

[siboy]

Thank you!
So how should I design my digital circuit's timing in my system. The digital part need the oscillator to offer as CLK. They need to be reset after power on. Does it mean my reset time must longer than the osc's start time?

 

[FvM]

The solution is a synchronous reset as already suggested. Instead of releasing the synchronous reset on the first clock edge, as usual, you can add some delay cycles by a counter. I'm generally using this technique (combined with an internal POR) for programmable logic if no external reset is available.

 

[siboy]

Thanks! FvM!
My opinion is similar with you. I've already designed a POR circuit which produce a reset pulse(Reset_POR) about 50us. And I will use a counter to count the clk_osc's posedge and produce another reset pulse(Reset_OSC).
Then do 'OR' operation to the two signals to get my finite reset : Reset=Reset_POR|Reset_OSC. That is the finite reset signal is the longer in the former two reset signals.
How do you think about it? And generally how many cycles should I count? I wish to get your opinion! Thanks very much!

 

[FvM]

I have only a small modification, instead of or-ing the external reset with the delay generator output, the external reset restarts the delay generator. It's similar to a usual synchronized reset in this aspect: asserted ansychronously, released synchronously.

 

[siboy]

So you means: no matter the external reset is long enough, you do add the delay to the reset time. Right?

Generally how many clk's cycles do you add?
Thank you very much!

 

[FvM]

The important point is, that I want to have a synchronous reset in any case. I'm using a few cycles only, but may be more for some application.