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HI,
i want to use random function in verilog HDL. i will have a set of numbers(6-8 in number) from which a random number has to be selected every time. suggest me the ways of implementing it.
Thanks Sharath. i used initial block in that module.
One more question.. I used a inout signal in one module. Now im calling that module from another module. I want to instantiate that module(which uses inout signal). here is my code.
Logic_Controller...
i have a verilog code for memory .I want to check read and write operation in it . i gave address and data. but i want to load memory register in it (before read and write ). probelem is mode reg is declared as register (not as any input or output).so in what form i shud give it in testbench. i...
In Cadence virtuoso 6.1.4, Mosfets are present in gpdk180 library. can anyone say me whether these mosfets conducts in subthreshold reigon ? i need a mosfet with low power consumption. in which library wil i get ?. what are te latest libraries which are advanced in technology .
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