Verilog coding - error correction in Xilinx platform

[shrikanthke]

My code is as follows:

---

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module StateMachine(
    input start,
    input CLK,
    input stop,
    input input_type,
    input read_to_read,
    output reg input_to_lc,
    output reg logic_controller_enable,
    output reg  read_enable,
    output reg mem_read
    
);
 
reg [1:0] state,next_state;
 
parameter S0 = 2'b00;
parameter S1 = 2'b01;
parameter S2 = 2'b10;
parameter S3 = 2'b11;
 
 
always@(posedge CLK or posedge stop )    
begin
    if(stop)
    state<=S0;                                                 //default state
    else if(start)
    state<=next_state;
end
 
always @(state )
begin
    
case(state)
    S0:
        begin
            if(start == 1'b1)
            begin
            $display("hiiii");
            state <= S1;
            end
            else 
            state <= S0;
        end
 
    S1:
        begin
            mem_read <= 1'b1;
            $display("hiiii  new");
            if(read_to_read == 1)
            state  <= S2;
            else 
            state<=S1;
 
        end
    
    S2:
        begin
            logic_controller_enable <= 1'b1;
            read_enable <= 1'b1;
            state <= S3;
        end
        
    S3:
        begin
        //  mem_write = 1'b1;
        end
    
    endcase
end
 
endmodule

---

when i try to synthesixe this, im getting error as multiple drivers on signal state. Error occurs at always@(posedge CLK...) block. how to correct this code..

 

[FvM]

Looks like a copy-and-paste error.

If you review the FSM templates in your text book, you'll notice that the always @(state) block should set next_state instead of state.

 

[ads-ee]

you'll notice that the always @(state) block should set next_state instead of state.

Which is a good reason to use the single clocked process FSM coding style as it avoids this pitfall.